Abstract: In one embodiment, a data storage system is provided may include an input/output (I/O) controller, and first and second memory boards. The controller may receive data and a request to store the data in the system, and may include memory for initially storing the data. The first memory board may store, in response to a first memory storage request, a first copy of the data initially stored in the controller. The first memory board may provide to the controller a first status indication indicating whether the first memory board successfully stored the first copy. The second memory board may store, in response to receipt of a second memory storage request, a second copy of the data. The controller may provide a second status indication, indicating whether the request to store the data in the system was successful.

Abstract: The invention is directed to techniques for transferring data within a data storage system that includes, among other things, an interconnection mechanism having a point-to-point channel between an interface circuit (e.g., a director) and a volatile memory cache circuit. The point-to-point channel allows the interface circuit and the volatile memory cache circuit to have contention free access to each other. One arrangement of the invention is directed to a data storage system having a volatile memory cache circuit that buffers data elements exchanged between a storage device and a host, an interface circuit that operates as an interface between the volatile memory cache circuit and at least one of a storage device and a host, and a point-to-point channel interconnected between the volatile memory cache circuit to the interface circuit.

Abstract: A data storage system for transferring data between a host computer/server and a bank of disk drives through a system interface. The system interface includes a backplane; a first printed circuit board plugged into a first side of the backplane; a second printed circuit board plugged into the first side of the backplane. The first and second printed circuit boards are disposed in an overlaying relationship. A third printed circuit board is plugged into a second side of the backplane. The second side is opposite to the first side. A memory having at least a first portion thereof is disposed on the third printed circuit board. A plurality of directors controls data transfer between the host computer and the bank of disk drives as such data passes through the memory. A first plurality of the directors is coupled to the host computer/server.

Abstract: A data storage system has storage devices, a processor which is configured to move data to and from the storage devices, and a bus coupled to the processor. The data storage system further includes a memory board having (i) an interface which couples to the bus, (ii) memory which is configured to store a doubly linked list data structure, and (iii) a memory board control circuit coupled to the interface and the memory. The memory board control circuit is capable of accessing the data structure. In particular, the memory board control circuit is configured to receive a modify command from the processor through the interface and the bus, atomically modify the data structure in accordance with the modify command, and provide a result to the processor through the interface and the bus in response to modifying the data structure.

Abstract: A cabinet having a plurality of rack mountable chassis. One portion of such chassis has directors and electrically interconnected memory and another portion of such chassis having a plurality of disk drives. The plurality of chassis are electrically interconnected to provide a data storage system interface. The another portion of the cabinets includes therein a printed circuit board having plugged into a surface thereof a plurality of disk drives. The cabinet includes a plurality of rack mountable chassis. A first one of such chassis has a memory and a plurality of directors for controlling data transfer between a host computer/server and a bank of disk drives as such data passes through the memory. A first plurality of the directors are for coupling to the host computer/server. A second plurality of the directors are for coupling to a bank of disk drives. A second one of such chassis has a plurality of disk drives, such disk drives being plugged into a surface of a printed circuit board.

Abstract: A cabinet having a plurality of rack mountable chassis. One portion of such chassis has directors and electrically interconnected memory and another portion of such chassis has a plurality of disk drives. The plurality of chassis are electrically interconnected to provide a data storage system interface. A first one of such chassis includes a memory and a plurality of directors. A first plurality of the directors is adapted for coupling to a host computer/server. A second one of such chassis has a plurality of disk drives. Also includes are first electrical conductors for connecting the disk drives in the second chassis to a second plurality of directors in the first one of the chassis. A third one of such chassis includes a memory and a plurality of directors. The first plurality of the directors in the third one of the chassis are adapted for coupling to the host computer/server. A fourth one of such chassis has a plurality of disk drives.

Abstract: In one embodiment of the present invention, a system is provided for use in transmitting data and related control information from a first clock domain to a second clock domain. The system may include a first logic section that may generate respective identification information that may be used to identify respective types of information represented by respective data and related control information. The system may also include memory that may receive and store, at a first clock rate used in the first clock domain, the respective data and related control information. The memory also may store, in association with the respective data and related control information, the respective identification information. The memory may be configured to permit the retrieval, at a second clock rate used in the second clock domain, of the respective data, the respective related control information, and the respective identification information stored in the memory.

Abstract: A system interface having a plurality of directors, one portion of such directors being adapted for coupling to a host computer/server and another portion of the directors being adapted for coupling to a bank of disk drives. The plurality of directors are interconnected through a network. A common resource section is provided having a resource shared among the plurality of directors. The common shared resource section includes a shared computer code used by the plurality of directors. The code includes computer code for booting up each one of the plurality directors. The common shared code storage section is interconnected to the directors through the network. A second, redundant common shared resource section is provided. The network is a packet switching network.

Abstract: A network adapter is provided that may be used in a network data storage system to facilitate data communication among external data exchanging devices and an input/output (I/O) controller residing in the system. The adapter includes one or more interfaces that may be coupled to an electrical backplane in the system. The backplane is coupled to the controller, and is configured to permit communication between the controller and the adapter when the interfaces are coupled to the backplane. The adapter may provide one or more file server-like behaviors.

Abstract: The invention is directed to data storage and retrieval techniques that utilize a cache which is preferred to a consumer of a data element stored within that cache. Since the cache is preferred to the consumer, the consumer has less contention for access to the preferred cache vis-à-vis a cache of a conventional data storage system implementation which is typically equally shared throughout the data storage system. Preferably, the preferred cache is on the same circuit board as the consumer so that memory accesses are on the order of a few hundred nanoseconds, rather than several microseconds when the cache and the consumer are on different circuit boards as in a conventional data storage implementation. One arrangement of the invention is directed to a data storage system having a first circuit board, a second circuit board and a connection mechanism that connects the first and second circuit boards together.

Abstract: An interrupt request controller for processing a plurality of interrupt logic signals. The controller includes: a programmable bit masking section fed by the interrupt logic signals, adapted to mask selected ones of the interrupt signals; a interrupt priority section fed by the programmable mask section for coupling unmasked ones of the interrupt signals to a plurality of outputs selectively in accordance with a predetermined priority criteria. The request controller includes: a programmable section fed by the interrupt signals, for selecting assertion sense and/or assertion type of each one of the interrupt signals. The programmable section stores a bit for each one of the interrupt logic signals representative of whether the logic state of the interrupt logic signal should be, or should not be, inverted and for producing a corresponding output logic interrupt signal in accordance therewith.

Abstract: The invention is directed to techniques for handling a client-oriented request within a data-storage system. Handling of a client-oriented request enables direct communication between a client and the system thus offloading any servers' burden of handling client requests. Furthermore, in some situations, such handling of the client-oriented request within the data storage system enables reduced traffic through the cache of the system, and reduced traffic between the system and external devices. In one arrangement, the data storage system includes a set of ports for connecting to an external host, a cache for buffering data exchanged between the external host and a set of storage devices, and a set of interface circuits including front-end interface circuits interconnected between the cache and the set of ports, and back-end interface circuits interconnected between the cache and the set of storage devices.

Abstract: An electronic system having a set of circuit boards and an interconnect. Each of the set of circuit boards includes a set of fiber optic circuit board connectors. The interconnect includes (i) a first planar member, (ii) a second planar member that is substantially parallel to the first planar member, and (iii) a set of fiber optic cable assemblies. Each fiber optic cable assembly includes a fiber optic cable segment, a first fiber optic interconnect connector which fastens to one end of that fiber optic cable segment and a second fiber optic interconnect connector which fastens to another end of that fiber optic cable segment. Each fiber optic interconnect connector extends through a hole defined by one of the first and second planar members. Furthermore, each fiber optic interconnect connector is configured to engage with a fiber optic circuit board connector.

Abstract: In one embodiment of the present invention, a system is provided for use in transmitting data and related control information from a first clock domain to a second clock domain. The system may include a first logic section that may generate respective identification information that may be used to identify respective types of information represented by respective data and related control information. The system may also include memory that may receive and store, at a first clock rate used in the first clock domain, the respective data and related control information. The memory also may store, in association with the respective data and related control information, the respective identification information. The memory may be configured to permit the retrieval, at a second clock rate used in the second clock domain, of the respective data, the respective related control information, and the respective identification information stored in the memory.

Abstract: The invention is directed to techniques for accessing data within a data storage system having a circuit board that includes both a front-end circuit for interfacing with a host and a back-end circuit for interfacing with a storage device. To move data between the host and the storage device, an exchange of data between the front-end circuit and the back-end circuit can occur within the circuit board thus circumventing the cache of the data storage system. Such operation not only reduces traffic through the cache, but also shortens the data transfer latency. In one arrangement, a data storage system includes a cache, a first front-end circuit that operates as an interface between the cache and a first host, a second front-end circuit that operates as an interface between the cache and a second host, a first storage device (e.g., a disk drive, tape drive, CDROM drive, etc.

Abstract: A storage cluster includes integrated cached disk arrays (ICDAs) and cluster interconnect such as a set of Fiber Channel links. Selected ICDAs include data storage disks collectively configured as cluster volumes. A switch network in each ICDA provides connections between the cluster interconnect and host interfaces, disk interfaces, and memory modules that may reside in the ICDA. Upon receiving a request, an ICDA determines whether the target disk resides in another ICDA, and if so forwards the request to the other ICDA via the cluster interconnect. The other ICDA services the request and returns a completion indication, which is forwarded to the host. Requests may also flow from the second ICDA to the first ICDA. The ICDAs may also include memory for data caching. The switch network preferably has a common interface to the different functional elements (host interfaces, disk interfaces, memory modules) for greater flexibility in configuring each ICDA.

Abstract: A storage cluster includes integrated cached disk arrays (ICDAs) and cluster interconnect such as a set of Fiber Channel links. Selected ICDAs include data storage disks collectively configured as cluster volumes. A switch network in each ICDA provides connections between the cluster interconnect and host interfaces, disk interfaces, and memory modules that may reside in the ICDA. Upon receiving a request, an ICDA determines whether the target disk resides in another ICDA, and if so forwards the request to the other ICDA via the cluster interconnect. The other ICDA services the request and returns a completion indication, which is forwarded to the host. Requests may also flow from the second ICDA to the first ICDA. The ICDAs may also include memory for data caching. The switch network preferably has a common interface to the different functional elements (host interfaces, disk interfaces, memory modules) for greater flexibility in configuring each ICDA.

Abstract: The invention is directed to data storage and retrieval techniques that utilize a cache which is preferred to a consumer of a data element stored within that cache. Since the cache is preferred to the consumer, the consumer has less contention for access to the preferred cache vis-à-vis a cache of a conventional data storage system implementation which is typically equally shared throughout the data storage system. Preferably, the preferred cache is on the same circuit board as the consumer so that memory accesses are on the order of a few hundred nanoseconds, rather than several microseconds when the cache and the consumer are on different circuit boards as in a conventional data storage implementation. One arrangement of the invention is directed to a data storage system having a first circuit board, a second circuit board and a connection mechanism that connects the first and second circuit boards together.

Abstract: The invention is directed to techniques for transferring data within a data storage system that includes, among other things, an interconnection mechanism having a point-to-point channel between an interface circuit (e.g., a director) and a volatile memory cache circuit. The point-to-point channel allows the interface circuit and the volatile memory cache circuit to have contention free access to each other. Such access is superior to the blocking nature of a conventional multi-drop bus topology data storage system. In particular, the contention free access provided by the invention essentially alleviates interconnection mechanism delays, e.g., delays due to other devices using the bus, delays due to bus allocation (e.g., bus arbitration cycles), etc. Furthermore, the point-to-point nature of communications between devices of the data storage system (e.g.