Patents by Inventor Kengo Aritomi

Kengo Aritomi has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Semiconductor memory device with a hierarchical word line configuration capable of preventing leakage current in a sub-word line driver
    Publication number: 20020001217
    Abstract: Complementary sub-decode signals to be provided to a sub-word line driver are separately generated through different circuits using individual power-supply voltages. Thus, the generation of a through current in the sub-word line driver is prevented.
    Type: Application
    Filed: May 8, 2000
    Publication date: January 3, 2002
    Inventors: Kengo Aritomi, Mikio Asakura, Takashi Ito, Kiyohiro Furutani
  • Semiconductor memory device with memory test circuit
    Publication number: 20010053086
    Abstract: A semiconductor memory device includes a plurality of array blocks including word lines, memory cells, bit lines, dummy word lines and transistors. In a test mode, rather than a word line a dummy word line is selected. Selectively turning on either one of the transistors allows a bit line connected thereto to be driven to a ground potential. Thus, a channel leak can be detected. In a mode other than the test mode, a defective word line is substituted by a spare word line included in a spare block.
    Type: Application
    Filed: December 15, 2000
    Publication date: December 20, 2001
    Applicant: Mitsubishi Denki Kabushiki Kaisha
    Inventors: Kengo Aritomi, Mikio Asakura
  • Semiconductor memory device with test mode decision circuit
    Patent number: 6269038
    Abstract: There is provided a test mode decision circuit which in the first WCBR cycle responds to an address key by activating a test mode entry signal and with the test mode entry signal activated in the second WCBR cycle responds to an address key by selectively activating test mode signals. In addition to a test mode signal having been activated, the test mode decision circuit further activates another test mode signal. Thus the DRAM hardly enter a test mode erroneously and is also capable of entering more than one test mode simultaneously.
    Type: Grant
    Filed: April 24, 2000
    Date of Patent: July 31, 2001
    Assignee: Mitsubishi Denki Kabushiki Kaisha
    Inventors: Takashi Itou, Yasuhiko Tsukikawa, Kengo Aritomi, Mikio Asakura