Abstract: Each of pixel regions of an active matrix substrate (1002) includes: a lower insulating layer (5); an oxide semiconductor layer (7) that is arranged on the lower insulating layer and includes an active region (7a) of an oxide semiconductor TFT; an upper insulating layer (9) that is arranged on a portion of the oxide semiconductor layer so as not to be in contact with the lower insulating layer; an upper gate layer (10) that is arranged on the upper insulating layer and includes an upper gate electrode (10a) and one of a plurality of gate bus lines (GL); and a source electrode and a drain electrode, wherein: the oxide semiconductor layer 7 further includes an extension region (7e) that extends from the active region (7a) in a direction x different from a channel length direction y of the oxide semiconductor TFT as seen from a normal direction to the substrate; and the extension region (7e) is arranged on the substrate side of one of the plurality of gate bus lines (GL) with an upper insulating layer (9) interp

Abstract: A substrate includes thin film transistors, each of which includes: an upper gate electrode formed of a first conductive film and continuous with one of gate lines; a source electrode formed of a second conductive film and continuous with one of source lines; a channel region formed of a portion of a semiconductor film over which an upper gate insulating film is disposed and overlapping the upper gate electrode; a source region formed of a portion of the semiconductor film and continuous with the channel region, and a drain region formed of a portion of the semiconductor film and continuous with the channel region on an opposite side of the channel region from the source region. The source electrode connects the source line and the source region through a first contact hole in an interlayer insulating film disposed over the first conductive film and containing a photosensitive material.

Abstract: An active matrix substrate is provided with a gate driver including a multi-stage shift register (240). Each stage of the multi-stage shift register has a plurality of oxide semiconductor TFTs, a first input terminal for receiving a set signal, a second input terminal for receiving a clock signal, a third input terminal for receiving a clear signal, and an output terminal for outputting a gate output signal to one of the plurality of gate bus lines. The clock signal and the clear signal have the same high-level potential, and the clock signal and the clear signal have the same low-level potential. The plurality of oxide semiconductor TFTs include a first TFT (101) having a back-gate structure. The main gate electrode of the first TFT (101) is coupled to the third input terminal or a negative power supply voltage VSS. The back-gate electrode of the first TFT has a potential set to a positive power supply voltage VDD or a ground potential GND.

Abstract: According to an embodiment of the present invention, an active matrix substrate (100) includes a display region (DR) defined by a plurality of pixel regions (P) arranged in a matrix and a peripheral region (FR) located around the display region. The active matrix substrate includes a substrate (1), a first TFT (10), and a second TFT (20). The first TFT is supported by the substrate and disposed in the peripheral region. The second TFT is supported by the substrate and disposed in the display region. The first TFT includes a crystalline silicon semiconductor layer (11), which is an active layer. The second TFT includes an oxide semiconductor layer (21), which is an active layer. The first TFT and the second TFT each have a top-gate structure.

Abstract: A method for manufacturing an active matrix substrate including a thin film transistor disposed for each pixel, and a first electrode and a first wiring line for touchscreen panel function includes: (A) a step of forming an oxide semiconductor layer, a gate insulating layer, and a gate electrode on a substrate; (B) a step of forming an insulating layer covering the gate electrode, the gate insulating layer, and the oxide semiconductor layer, and having a source-side aperture and a drain-side aperture through which portions of the oxide semiconductor layer are exposed; (C) a step of forming a source electrode within the source-side aperture and a drain electrode within the drain-side aperture; (D) a step of forming an interlayer insulating layer including an organic insulating layer and having a first contact hole through which a portion of the drain electrode is exposed; (E) a step of forming a first transparent electrically conductive film on the interlayer insulating layer and within the first contact hole;

Abstract: A semiconductor device includes a substrate and an oxide semiconductor TFT including an oxide semiconductor layer supported by the substrate and having a multilayer structure including a protective oxide semiconductor layer and a channel oxide semiconductor layer disposed closer to the substrate than the protective oxide semiconductor layer, an upper insulating layer on the oxide semiconductor layer, an upper gate electrode disposed on the upper insulating layer, an interlayer insulating layer covering the oxide semiconductor layer and the upper gate electrode, and first and second electrodes electrically connected to the oxide semiconductor layer, wherein a first opening extends through at least the interlayer insulating layer and the protective oxide semiconductor layer, and exposes a portion of the channel oxide semiconductor layer, and the first electrode is disposed on the interlayer insulating layer and within the first opening, and is in direct contact with, within the first opening, the portion.

Abstract: [Object] To provide an active matrix substrate (1) that includes an organic insulating film (OIL) and first source layers (FSL2 to FSL4) and second source layers (SSL1 to SSL3), which constitute two-layer wiring lines, and that is produced with a high yield. [Solution] In an active matrix substrate (1), of the first source layers (FSL2 to FSL4) and the second source layers (SSL1 to SSL3), the second source layers (SSL1 to SSL3) arranged further from the substrate (2) are in contact with an organic insulating film (OIL) with a second inorganic insulating film (SINOIL) interposed therebetween.

Abstract: Provided is an active matrix substrate (100A) including: a gate metal layer (15) that has a two-layer structure composed of a Cu layer (15b) and a Ti layer (15a); a first insulating layer (16) on the gate metal layer (15); a source metal layer (18) that is formed on the first insulating layer (16) and has a two-layer structure composed of a Cu layer (18b) and a Ti layer (18a); a second insulating layer (19) on the source metal layer (18); a conductive layer (25) that is formed on the second insulating layer (19), and is in contact with the gate metal layer (15) within a first opening (16a1) formed in the first insulating layer (16) and is in contact with the source metal layer (18) within a second opening (19a2) formed in the second insulating layer (19); and a first transparent conductive layer (21) that is formed on the conductive layer (25) and includes any of a pixel electrode, a common electrode and an auxiliary capacitor electrode.

Abstract: A semiconductor device includes a first TFT, a first source-side connection section that is formed from a part of a second metal film and connected to a first source region, a first drain-side connection section that is formed from a part of the second metal film and connected to a first drain region, a second TFT that is driven by the first TFT, a second source-side connection section that is formed from a part of a first metal film and connected to a second source region, and a second drain-side connection section that is formed from a part of the first metal film or a second transparent electrode film and connected to a second drain region.

Abstract: A thin film transistor substrate includes a source line, a gate electrode, a channel region, a source region, a drain region, and a pixel electrode. The gate electrode is a portion of a first metal film disposed upper than a first insulating film that is disposed upper than a semiconductor film. The source line is a portion of a second metal film disposed upper than a second insulating film that is disposed upper than the first metal film. The channel region is a portion of a section of the semiconductor film and disposed to overlap the gate electrode. The source region is prepared by reducing a resistance of a section of the semiconductor film. The drain region is prepared by reducing a resistance of a section of the semiconductor film. The pixel electrode is prepared by reducing a resistance of a section of the semiconductor film.

Abstract: An active matrix substrate according to an embodiment of the present invention includes a plurality of thin film transistors supported on a substrate and an inorganic insulating layer covering the plurality of thin film transistors. Each thin film transistor includes a gate electrode, an oxide semiconductor layer, a gate insulating layer, a source electrode, and a drain electrode. At least one of the gate insulating layer and the inorganic insulating layer is an insulating layer stack having a multilayer structure including a silicon oxide layer and a silicon nitride layer. The insulating layer stack further includes an intermediate layer disposed between the silicon oxide layer and the silicon nitride layer, the intermediate layer having a refractive index nC higher than a refractive index nA of the silicon oxide layer and lower than a refractive index nB of the silicon nitride layer.

Abstract: An oxide semiconductor TFT (201) of an active matrix substrate includes an oxide semiconductor layer (107), an upper gate electrode (112) disposed on a part of the oxide semiconductor layer via a gate insulating layer, and a source electrode (113) and a drain electrode (114). As viewed from a normal direction of the substrate, the oxide semiconductor layer (107) includes a first portion (p1) that overlaps the upper gate electrode, and a second portion (p2) that is located between the first portion and the source contact region or drain contact region, such that the gate insulating layer does not cover the second portion. The upper gate electrode (112) has a multilayer structure including an alloy layer (112L) that is in contact with the gate insulating layer and a metal layer (112U) that is disposed on the alloy layer. The metal layer is made of a first metallic element M; the alloy layer is made of an alloy containing the first metallic element M; and the first metallic element M is Cu, Mo, or Cr.

Abstract: A semiconductor device includes a thin film transistor including a semiconductor layer, a gate electrode, a gate insulating layer, a source electrode, a drain electrode, the semiconductor layer includes a layered structure including a first oxide semiconductor layer including In and Zn, in which an atomic ratio of In with respect to all metallic elements included in the first oxide semiconductor layer is higher than an atomic ratio of Zn, a second oxide semiconductor layer including In and Zn, in which an atomic ratio of Zn with respect to all metallic elements included in the second oxide semiconductor layer is higher than an atomic ratio of In, and an intermediate oxide semiconductor layer arranged between the first oxide semiconductor layer and the second oxide semiconductor layer, and the first and second oxide semiconductor layers are crystalline oxide semiconductor layers, and the intermediate oxide semiconductor layer is an amorphous oxide semiconductor layer, and the first oxide semiconductor layer is

Abstract: A semiconductor device includes a thin film transistor, wherein: a semiconductor layer of the thin film transistor has a layered structure including a lower oxide semiconductor layer including In, Ga, Zn and Sn and an upper oxide semiconductor layer arranged on the lower oxide semiconductor layer and including In, Ga and Zn; a thickness of the lower oxide semiconductor layer is 20 nm or less; an atomic ratio of Sn with respect to all metal elements of the lower oxide semiconductor layer is 5% or more; the upper oxide semiconductor layer includes no Sn, or an atomic ratio of Sn with respect to all metal elements of the upper oxide semiconductor layer is smaller than an atomic ratio of Sn with respect to all metal elements of the lower oxide semiconductor layer; and a first angle ?1 between a side surface and a lower surface of the lower oxide semiconductor layer is smaller than a second angle ?2 between a side surface and a lower surface of the upper oxide semiconductor layer.

Abstract: A thin film transistor includes a channel section formed from semiconductor material, a source electrode connected to one end of the channel section, a drain electrode connected to another end of the channel section, an upper gate electrode included in an upper layer than the channel section and overlapping the channel section, a lower gate electrode included in a lower layer than the channel section and overlapping the channel section, an upper gate insulation film disposed between the upper gate electrode and the channel section, and a lower gate insulation film disposed between the lower gate electrode and the channel section and having a film thickness relatively greater than that of the upper gate insulation film.

Abstract: An active matrix substrate is provided with a gate driver including a multi-stage shift register (240). Each stage of the multi-stage shift register has a plurality of oxide semiconductor TFTs, a first input terminal for receiving a set signal, a second input terminal for receiving a clock signal, a third input terminal for receiving a clear signal, and an output terminal for outputting a gate output signal to one of the plurality of gate bus lines. The clock signal and the clear signal have the same high-level potential, and the clock signal and the clear signal have the same low-level potential. The plurality of oxide semiconductor TFTs include a first TFT (101) having a back-gate structure. The main gate electrode of the first TFT (101) is coupled to the third input terminal or a negative power supply voltage VSS. The back-gate electrode of the first TFT has a potential set to a positive power supply voltage VDD or a ground potential GND.

Abstract: A semiconductor device includes a substrate and an oxide semiconductor TFT including an oxide semiconductor layer supported by the substrate and having a multilayer structure including a protective oxide semiconductor layer and a channel oxide semiconductor layer disposed closer to the substrate than the protective oxide semiconductor layer, an upper insulating layer on the oxide semiconductor layer, an upper gate electrode disposed on the upper insulating layer, an interlayer insulating layer covering the oxide semiconductor layer and the upper gate electrode, and first and second electrodes electrically connected to the oxide semiconductor layer, wherein a first opening extends through at least the interlayer insulating layer and the protective oxide semiconductor layer, and exposes a portion of the channel oxide semiconductor layer, and the first electrode is disposed on the interlayer insulating layer and within the first opening, and is in direct contact with, within the first opening, the portion.

Abstract: An output control node stabilization portion includes a thin film transistor having a gate terminal to which is provided a fourth clock that changes to an on level at timing at which a scanning signal outputted from a previous stage is to change from an off level to an on level, a drain terminal connected to an output control node, and a source terminal to which the scanning signal outputted from the previous stage is provided; and a thin film transistor having a gate terminal to which is provided a third clock that changes to an on level at timing at which a scanning signal outputted from a subsequent stage is to change from an off level to an on level, a drain terminal connected to the output control node, and a source terminal to which the scanning signal outputted from the subsequent stage is provided.

Abstract: An array substrate including a spin-on glass layer formed of spin-on glass material, a first line disposed on a lower side with respect to the spin-on glass layer, the first line including a copper containing layer formed of copper or a copper alloy and a metal upper layer formed of one selected from a group consisting of titanium, an aluminum alloy, a copper alloy, a tungsten alloy, and a tantalum alloy, and the metal upper layer disposed on the copper containing layer and disposed between the copper containing layer and the spin-on glass layer, and a second line disposed on an upper side with respect to the spin-on glass layer and overlapping the first line in a plan view.

Abstract: A TFT array substrate includes gate electrodes constructed from a first metal film, a first insulating film on the first metal film, channels constructed from a semiconductor film on the first insulating film, source electrodes constructed from a second metal film on the semiconductor film, drain electrodes constructed from the second metal film, pixel electrodes constructed from portions of the semiconductor film having reduced resistances, a second insulating film on the semiconductor film and the second metal film, and a common electrode constructed from a transparent electrode film on the second insulating film. The channels overlap the gate electrodes. The source electrodes and the drain electrodes are connected to first ends and second ends of the channels, respectively. The pixel electrodes are connected to the drain electrodes. The second insulating film includes sections overlapping the pixel electrodes without openings. The common electrode overlaps at least the pixel electrodes.