Patents by Inventor Kengo Inoue
Kengo Inoue has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20170260534Abstract: The object of the invention is to provide an anaerobic enterobacterium having a higher therapeutic effect on an anaerobic site such as a solid tumor tissue and an ischemic disease site. A bacterium of the genus Bifidobacterium, which is transformed with a plasmid co-expressing two types of heterologous polypeptides and comprising two types of secretory expression cassettes each sequentially comprising a promoter DNA functioning in the bacterium of the genus Bifidobacterium; a DNA encoding a secretory signal peptide; a DNA encoding a heterologous polypeptide; and a terminator DNA functioning in the bacterium of the genus Bifidobacterium, efficiently secretes the two types of heterologous peptides, i.e., two types of antibodies having anticancer effects, outside the bacterial cell.Type: ApplicationFiled: December 2, 2015Publication date: September 14, 2017Inventors: Koichi KOSEKI, Koichiro SHIOYA, Satoshi KOBAYASHI, Yuko SHIMATANI, Takeshi MASAKI, Hitomi SHIMIZU, Tomio MATSUMURA, Masami OKABE, Kengo INOUE
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Publication number: 20160240543Abstract: A semiconductor device manufacturing method includes: forming an element isolation insulating film in a semiconductor substrate; forming a first film on a surface of the semiconductor substrate; forming a second film on the element isolation insulating film and on the first film; forming a first resist pattern that includes a first open above the element isolation insulating film in a first region; removing the second film on the element isolation insulating film in the first region to separate the second film in the first region into a plurality of parts by performing first etching; forming a third film on the second film in the first region; forming a first gate electrode on the third film in the first region; and forming a first insulating film that includes the first to third films under the first gate electrode by patterning the first to third films.Type: ApplicationFiled: April 21, 2016Publication date: August 18, 2016Inventors: Satoshi Torii, Hideaki Matsumura, Hikaru Kokura, Etsuro Kawaguchi, Katsuaki Ookoshi, Yuka Kase, Kengo Inoue
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Patent number: 9349600Abstract: A semiconductor device manufacturing method includes: forming an element isolation insulating film in a semiconductor substrate; forming a first film on a surface of the semiconductor substrate; forming a second film on the element isolation insulating film and on the first film; forming a first resist pattern that includes a first open above the element isolation insulating film in a first region; removing the second film on the element isolation insulating film in the first region to separate the second film in the first region into a plurality of parts by performing first etching; forming a third film on the second film in the first region; forming a first gate electrode on the third film in the first region; and forming a first insulating film that includes the first to third films under the first gate electrode by patterning the first to third films.Type: GrantFiled: November 19, 2014Date of Patent: May 24, 2016Assignee: FUJITSU SEMICONDUCTOR LIMITEDInventors: Satoshi Torii, Hideaki Matsumura, Hikaru Kokura, Etsuro Kawaguchi, Katsuaki Ookoshi, Yuka Kase, Kengo Inoue
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Publication number: 20160060235Abstract: An object of the present invention is to provide a novel therapeutic agent for a patient with type 2 diabetes, a cause of which is the abnormal synthesis of insulin attributed to the abnormal modification of tRNALys (UUU) in pancreatic ? cells having Cdkal1 gene mutation. The present inventors have used (1) a screening system using E. coli in which correct translation into luciferase requires frameshift resulting from mistranslation during protein translation, (2) a screening system using the pancreatic islet of Langerhans isolated from a pancreatic ? cell-specific Cdkal1-deficient mouse, and (3) a screening system using a pancreatic ? cell-specific Cdkal1-deficient mouse, and found that a compound represented by any of the following formulas (I) to (III) can serve as a therapeutic agent for a patient with type 2 diabetes with Cdkal1 gene mutation resulting in the reduced ability to secrete insulin.Type: ApplicationFiled: March 28, 2014Publication date: March 3, 2016Inventors: Kazuhito Tomizawa, Fanyan Wei, Kengo Inoue, Tadashi Okawara
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Publication number: 20150137211Abstract: A semiconductor device manufacturing method includes: forming an element isolation insulating film in a semiconductor substrate; forming a first film on a surface of the semiconductor substrate; forming a second film on the element isolation insulating film and on the first film; forming a first resist pattern that includes a first open above the element isolation insulating film in a first region; removing the second film on the element isolation insulating film in the first region to separate the second film in the first region into a plurality of parts by performing first etching; forming a third film on the second film in the first region; forming a first gate electrode on the third film in the first region; and forming a first insulating film that includes the first to third films under the first gate electrode by patterning the first to third films.Type: ApplicationFiled: November 19, 2014Publication date: May 21, 2015Inventors: Satoshi TORII, Hideaki MATSUMURA, Hikaru KOKURA, Etsuro KAWAGUCHI, Katsuaki OOKOSHI, Yuka KASE, Kengo INOUE
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Patent number: 8778814Abstract: A method of manufacturing a semiconductor device includes the steps of: preparing an underlying structure having a silicon carbide layer covering a copper wiring, and growing silicon oxycarbide on the underlying structure by vapor deposition using, as source gas, tetramethylcyclotetrasiloxane, carbon dioxide gas and oxygen gas, a flow rate of said oxygen gas being at most 3% of a flow rate of the carbon dioxide gas. The surface of the silicon carbide layer of the underlying structure may be treated with a plasma of weak oxidizing gas which contains oxygen and has a molecular weight larger than that of O2 to bring the surface more hydrophilic. Film peel-off and cracks in the interlayer insulating layer decrease.Type: GrantFiled: August 14, 2013Date of Patent: July 15, 2014Assignee: Fujitsu Semiconductor LimitedInventors: Tamotsu Owada, Shun-ichi Furuyama, Hirofumi Watantani, Kengo Inoue, Atsuo Shimizu
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Publication number: 20130330912Abstract: A method of manufacturing a semiconductor device includes the steps of: preparing an underlying structure having a silicon carbide layer covering a copper wiring, and growing silicon oxycarbide on the underlying structure by vapor deposition using, as source gas, tetramethylcyclotetrasiloxane, carbon dioxide gas and oxygen gas, a flow rate of said oxygen gas being at most 3% of a flow rate of the carbon dioxide gas. The surface of the silicon carbide layer of the underlying structure may be treated with a plasma of weak oxidizing gas which contains oxygen and has a molecular weight larger than that of O2 to bring the surface more hydrophilic. Film peel-off and cracks in the interlayer insulating layer decrease.Type: ApplicationFiled: August 14, 2013Publication date: December 12, 2013Applicant: FUJITSU SEMICONDUCTOR LIMITEDInventors: Tamotsu Owada, Shun-ichi Furuyama, Hirofumi Watatani, Kengo Inoue, Atsuo Shimizu
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Patent number: 8352219Abstract: The object is to enable the calculation of load transfer paths in case of distributed load applied to the structure with the numerical structure-analysis calculation system. The value of the parameter U** at each point is calculated according to the ratio of the complementary strain energy U at the application of load without fixing the point in the structure and the complementary strain energy U? at the application of load with fixing one point in the structure. In the actual calculation, according to the complementary strain energy U, and the flexibility matrix CAC with respect to the loading point A and one point C in the structure, and the inverse matrix CCC?1 of the flexibility matrix with respect to point C, and the load pA at the loading point A, the value of the parameter U** (CACCCC?1CCApA·pA/(2U)) at point C is calculated.Type: GrantFiled: February 4, 2008Date of Patent: January 8, 2013Assignee: Keio UniversityInventors: Kunihiro Takahashi, Toshiaki Sakurai, Tatsuya Nakada, Kengo Inoue
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Patent number: 8349722Abstract: A method of manufacturing a semiconductor device includes the steps of: preparing an underlying structure having a silicon carbide layer covering a copper wiring, and growing silicon oxycarbide on the underlying structure by vapor deposition using, as source gas, tetramethylcyclotetrasiloxane, carbon dioxide gas and oxygen gas, a flow rate of said oxygen gas being at most 3% of a flow rate of the carbon dioxide gas. The surface of the silicon carbide layer of the underlying structure may be treated with a plasma of weak oxidizing gas which contains oxygen and has a molecular weight larger than that of O2 to bring the surface more hydrophilic. Film peel-off and cracks in the interlayer insulating layer decrease.Type: GrantFiled: December 3, 2008Date of Patent: January 8, 2013Assignee: Fujitsu Semiconductor LimitedInventors: Tamotsu Owada, Shun-ichi Fukuyama, Hirofumi Watatani, Kengo Inoue, Atsuo Shimizu
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Publication number: 20120252227Abstract: A method of manufacturing a semiconductor device includes the steps of: preparing an underlying structure having a silicon carbide layer covering a copper wiring, and growing silicon oxycarbide on the underlying structure by vapor deposition using, as source gas, tetramethylcyclotetrasiloxane, carbon dioxide gas and oxygen gas, a flow rate of said oxygen gas being at most 3% of a flow rate of the carbon dioxide gas. The surface of the silicon carbide layer of the underlying structure may be treated with a plasma of weak oxidizing gas which contains oxygen and has a molecular weight larger than that of O2 to bring the surface more hydrophilic. Film peel-off and cracks in the interlayer insulating layer decrease.Type: ApplicationFiled: June 11, 2012Publication date: October 4, 2012Applicant: FUJITSU SEMICONDUCTOR LIMITEDInventors: Tamotsu Owada, Shun-ichi Fukuyama, Hirofumi Watatani, Kengo Inoue, Atsuo Shimizu
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Publication number: 20100100361Abstract: The object is to enable the calculation of load transfer paths in case of distributed load applied to the structure with the numerical structure-analysis calculation system. The value of the parameter U** at each point is calculated according to the ratio of the complementary strain energy U at the application of load without fixing the point in the structure and the complementary strain energy U? at the application of load with fixing one point in the structure. In the actual calculation, according to the complementary strain energy U, and the flexibility matrix CAC with respect to the loading point A and one point C in the structure, and the inverse matrix CCC?1 of the flexibility matrix with respect to point C, and the load pA at the loading point A, the value of the parameter U** (CACCCC?1CCApA·pA/(2U))at point C is calculated.Type: ApplicationFiled: February 4, 2008Publication date: April 22, 2010Applicant: KEIO UNIVERSITYInventors: Kunihiro Takasashi, Toshiaki Sakurai, Tatsuya Nakada, Kengo Inoue
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Patent number: 7626234Abstract: A semiconductor device manufacturing method includes the steps of: (a) forming a stopper layer for chemical mechanical polishing on a surface of a semiconductor substrate; (b) forming an element isolation trench in the stopper layer and the semiconductor substrate; (c) depositing a nitride film covering an inner surface of the trench; (d) depositing a first oxide film through high density plasma CVD, the first oxide film burying at least a lower portion of the trench deposited with the nitride film; (e) washing out the first oxide film on a side wall of the trench by dilute hydrofluoric acid; (f) depositing a second oxide film by high density plasma CVD, the second oxide film burying the trench after the washing-out; and (g) removing the oxide films on the stopper layer by chemical mechanical polishing.Type: GrantFiled: May 9, 2006Date of Patent: December 1, 2009Assignee: Fujitsu Microelectronics LimitedInventors: Kengo Inoue, Hiroyuki Ota
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Publication number: 20090093130Abstract: A method of manufacturing a semiconductor device includes the steps of: preparing an underlying structure having a silicon carbide layer covering a copper wiring, and growing silicon oxycarbide on the underlying structure by vapor deposition using, as source gas, tetramethylcyclotetrasiloxane, carbon dioxide gas and oxygen gas, a flow rate of said oxygen gas being at most 3% of a flow rate of the carbon dioxide gas. The surface of the silicon carbide layer of the underlying structure may be treated with a plasma of weak oxidizing gas which contains oxygen and has a molecular weight larger than that of O2 to bring the surface more hydrophilic. Film peel-off and cracks in the interlayer insulating layer decrease.Type: ApplicationFiled: December 3, 2008Publication date: April 9, 2009Applicant: FUJITSU LIMITEDInventors: Tamotsu Owada, Shun-ichi Fukuyama, Hirofumi Watatani, Kengo Inoue, Atsuo Shimizu
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Patent number: 7485570Abstract: A method of manufacturing a semiconductor device includes the steps of: preparing an underlying structure having a silicon carbide layer covering a copper wiring, and growing silicon oxycarbide on the underlying structure by vapor deposition using, as source gas, tetramethylcyclotetrasiloxane, carbon dioxide gas and oxygen gas, a flow rate of said oxygen gas being at most 3% of a flow rate of the carbon dioxide gas. The surface of the silicon carbide layer of the underlying structure may be treated with a plasma of weak oxidizing gas which contains oxygen and has a molecular weight larger than that of O2 to bring the surface more hydrophilic. Film peel-off and cracks in the interlayer insulating layer decrease.Type: GrantFiled: August 19, 2005Date of Patent: February 3, 2009Assignee: Fujitsu LimitedInventors: Tamotsu Owada, Shun-ichi Fukuyama, Hirofumi Watatani, Kengo Inoue, Atsuo Shimizu
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Patent number: 7211480Abstract: A semiconductor device manufacturing method includes the steps of: (a) forming a stopper layer for chemical mechanical polishing on a surface of a semiconductor substrate; (b) forming an element isolation trench in the stopper layer and the semiconductor substrate; (c) depositing a nitride film covering an inner surface of the trench; (d) depositing a first oxide film through high density plasma CVD, the first oxide film burying at least a lower portion of the trench deposited with the nitride film; (e) washing out the first oxide film on a side wall of the trench by dilute hydrofluoric acid; (f) depositing a second oxide film by high density plasma CVD, the second oxide film burying the trench after the washing-out; and (g) removing the oxide films on the stopper layer by chemical mechanical polishing.Type: GrantFiled: July 2, 2004Date of Patent: May 1, 2007Assignee: Fujitsu LimitedInventors: Kengo Inoue, Hiroyuki Ota
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Patent number: 7183200Abstract: A semiconductor device has a multi-layer interconnection structure with a first interlayer insulation film and a second interlayer insulation film that is formed on the first interlayer insulation film and has a hardness and an elastic modulus larger than those of the first interlayer insulation film, and is fabricated by a step of forming a resist film on the second interlayer insulation film via an antireflective film, a step of exposing to light and developing the resist film to form a resist pattern, and a step of patterning the antireflective film and the multi-layer interconnection structure using the resist pattern as a mask, wherein a film with no stress or for storing compressive stress is used as the antireflective film.Type: GrantFiled: February 28, 2005Date of Patent: February 27, 2007Assignee: Fujitsu LimitedInventor: Kengo Inoue
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Publication number: 20060255426Abstract: A semiconductor device manufacturing method includes the steps of: (a) forming a stopper layer for chemical mechanical polishing on a surface of a semiconductor substrate; (b) forming an element isolation trench in the stopper layer and the semiconductor substrate; (c) depositing a nitride film covering an inner surface of the trench; (d) depositing a first oxide film through high density plasma CVD, the first oxide film burying at least a lower portion of the trench deposited with the nitride film; (e) washing out the first oxide film on a side wall of the trench by dilute hydrofluoric acid; (f) depositing a second oxide film by high density plasma CVD, the second oxide film burying the trench after the washing-out; and (g) removing the oxide films on the stopper layer by chemical mechanical polishing.Type: ApplicationFiled: May 9, 2006Publication date: November 16, 2006Applicant: FUJITSU LIMITEDInventors: Kengo Inoue, Hiroyuki Ota
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Publication number: 20060205193Abstract: The method for forming an SiC-based film comprises the step of generating NH3 plasma on the surface of a substrate 20 in a chamber to make NH3 plasma processing on the substrate 20, the step of removing reaction products containing nitrogen remaining in the chamber, and the step of forming an SiC film 34 on the substrate 20 by PECVD.Type: ApplicationFiled: September 8, 2005Publication date: September 14, 2006Applicant: FUJITSU LIMITEDInventors: Ken Sugimoto, Yoshiyuki Ohkura, Hirofumi Watatani, Tamotsu Owada, Kengo Inoue
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Patent number: 7037803Abstract: A semiconductor device manufacture method has the steps of: (a) forming a polishing stopper layer over a semiconductor substrate; (b) etching the semiconductor substrate to form a trench; (c) forming a first liner insulating layer of silicon oxide over the surface of the trench; (d) forming a second liner insulating layer of silicon nitride over the first liner insulating layer, the second liner insulating layer having a thickness of at least 20 nm or at most 8 nm; (e1) depositing a third liner insulating layer of silicon oxide over the second liner insulating layer by plasma CVD at a first bias; and (e2) depositing an isolation layer of silicon oxide by plasma CVD at a second bias higher than the first bias, the isolation layer burying a recess defined by the third liner insulating layer.Type: GrantFiled: November 26, 2003Date of Patent: May 2, 2006Assignee: Fujitsu LimitedInventors: Kengo Inoue, Toshifumi Mori, Ryou Nakamura, Hiroyuki Ohta, Takashi Saiki
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Publication number: 20050287790Abstract: A method of manufacturing a semiconductor device includes the steps of: preparing an underlying structure having a silicon carbide layer covering a copper wiring, and growing silicon oxycarbide on the underlying structure by vapor deposition using, as source gas, tetramethylcyclotetrasiloxane, carbon dioxide gas and oxygen gas, a flow rate of said oxygen gas being at most 3% of a flow rate of the carbon dioxide gas. The surface of the silicon carbide layer of the underlying structure may be treated with a plasma of weak oxidizing gas which contains oxygen and has a molecular weight larger than that of O2 to bring the surface more hydrophilic. Film peel-off and cracks in the interlayer insulating layer decrease.Type: ApplicationFiled: August 19, 2005Publication date: December 29, 2005Applicant: FUJITSU LIMITEDInventors: Tamotsu Owada, Shun-ichi Fukuyama, Hirofumi Watatani, Kengo Inoue, Atsuo Shimizu