Patents by Inventor Kengo Kajiwara
Kengo Kajiwara has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20240099014Abstract: At least one vertically alternating sequence of continuous insulating layers and continuous sacrificial material layers is formed over a substrate. Rows of backside support pillar structures are formed through the at least one vertically alternating sequence. Memory stack structures are formed through the at least one vertically alternating sequence. A two-dimensional array of discrete backside trenches is formed through the at least one vertically alternating sequence. Contiguous combinations of a subset of the backside trenches and a subset of the backside support pillar structures divide the at least one vertically alternating sequence into alternating stacks of insulating layers and sacrificial material layers. The sacrificial material layers are replaced with electrically conductive layers while the backside support pillar structures provide structural support to the insulating layers.Type: ApplicationFiled: November 30, 2023Publication date: March 21, 2024Inventors: Shunsuke TAKUMA, Yuji TOTOKI, Seiji SHIMABUKURO, Tatsuya HINOUE, Kengo KAJIWARA, Akihiro TOBIOKA
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Patent number: 11844222Abstract: At least one vertically alternating sequence of continuous insulating layers and continuous sacrificial material layers is formed over a substrate. Rows of backside support pillar structures are formed through the at least one vertically alternating sequence. Memory stack structures are formed through the at least one vertically alternating sequence. A two-dimensional array of discrete backside trenches is formed through the at least one vertically alternating sequence. Contiguous combinations of a subset of the backside trenches and a subset of the backside support pillar structures divide the at least one vertically alternating sequence into alternating stacks of insulating layers and sacrificial material layers. The sacrificial material layers are replaced with electrically conductive layers while the backside support pillar structures provide structural support to the insulating layers.Type: GrantFiled: January 12, 2021Date of Patent: December 12, 2023Assignee: SANDISK TECHNOLOGIES LLCInventors: Shunsuke Takuma, Yuji Totoki, Seiji Shimabukuro, Tatsuya Hinoue, Kengo Kajiwara, Akihiro Tobioka
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Patent number: 11637119Abstract: A row of backside support pillar structures is formed through a first-tier alternating stack of first-tier insulating layers and first-tier sacrificial material layers. At least one upper-tier alternating stack can be formed, and memory stack structures can be formed through the alternating stacks. A backside trench can be formed through the alternating stacks selective to the row of backside support pillar structures. The sacrificial material layers are replaced with electrically conductive layers, and the backside trench can be filled with a backside trench fill structure, which includes the row of backside support pillar structures. The row of backside support pillar structures reduces or prevents tilting or collapse of the alternating stacks during replacement of the sacrificial material layers with the electrically conductive layers.Type: GrantFiled: December 28, 2020Date of Patent: April 25, 2023Assignee: SANDISK TECHNOLOGIES LLCInventors: Kohei Yamaguchi, Keisuke Shigemura, Kengo Kajiwara
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Patent number: 11637118Abstract: A alternating stack of insulating layers and sacrificial material layers is formed over a substrate. An array of memory opening fill structures and an array of support pillar structures are formed through the alternating stack. Backside trenches are formed through the alternating stack by performing an anisotropic etch process. The anisotropic etch process etches peripheral portions of a subset of the array of support pillar structures. The sacrificial material layers are replaced with electrically conductive layer by forming backside recesses while the support pillar structures provide mechanical support to the insulating layers.Type: GrantFiled: September 29, 2020Date of Patent: April 25, 2023Assignee: SANDISK TECHNOLOGIES LLCInventors: Shunsuke Takuma, Seiji Shimabukuro, Kengo Kajiwara
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Patent number: 11398497Abstract: A three-dimensional memory device includes a first-tier structure located over a substrate and including a first alternating stack of first insulating layers and first electrically conductive layers. a second-tier structure located over the first-tier structure and including a second alternating stack of second insulating layers and second electrically conductive layers, memory stack structures vertically extending through the first alternating stack and the second alternating stack, primary support pillar structures, and auxiliary support pillar structures vertically extending through the first alternating stack, underlying the second stepped surfaces, and located below a horizontal plane including a bottommost surface of the second alternating stack.Type: GrantFiled: May 18, 2020Date of Patent: July 26, 2022Assignee: SANDISK TECHNOLOGIES LLCInventors: Kengo Kajiwara, Atsushi Shimoda, Tatsuya Hinoue, Junpei Kanazawa, Masanori Terahara
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Publication number: 20220223614Abstract: At least one vertically alternating sequence of continuous insulating layers and continuous sacrificial material layers is formed over a substrate. Rows of backside support pillar structures are formed through the at least one vertically alternating sequence. Memory stack structures are formed through the at least one vertically alternating sequence. A two-dimensional array of discrete backside trenches is formed through the at least one vertically alternating sequence. Contiguous combinations of a subset of the backside trenches and a subset of the backside support pillar structures divide the at least one vertically alternating sequence into alternating stacks of insulating layers and sacrificial material layers. The sacrificial material layers are replaced with electrically conductive layers while the backside support pillar structures provide structural support to the insulating layers.Type: ApplicationFiled: January 12, 2021Publication date: July 14, 2022Inventors: Shunsuke TAKUMA, Yuji TOTOKI, Seiji SHIMABUKURO, Tatsuya HINOUE, Kengo KAJIWARA, Akihiro TOBIOKA
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Publication number: 20210358937Abstract: A row of backside support pillar structures is formed through a first-tier alternating stack of first-tier insulating layers and first-tier sacrificial material layers. At least one upper-tier alternating stack can be formed, and memory stack structures can be formed through the alternating stacks. A backside trench can be formed through the alternating stacks selective to the row of backside support pillar structures. The sacrificial material layers are replaced with electrically conductive layers, and the backside trench can be filled with a backside trench fill structure, which includes the row of backside support pillar structures. The row of backside support pillar structures reduces or prevents tilting or collapse of the alternating stacks during replacement of the sacrificial material layers with the electrically conductive layers.Type: ApplicationFiled: December 28, 2020Publication date: November 18, 2021Inventors: Kohei YAMAGUCHI, Keisuke SHIGEMURA, Kengo KAJIWARA
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Publication number: 20210358941Abstract: A three-dimensional memory device includes a first-tier structure located over a substrate and including a first alternating stack of first insulating layers and first electrically conductive layers. a second-tier structure located over the first-tier structure and including a second alternating stack of second insulating layers and second electrically conductive layers, memory stack structures vertically extending through the first alternating stack and the second alternating stack, primary support pillar structures, and auxiliary support pillar structures vertically extending through the first alternating stack, underlying the second stepped surfaces, and located below a horizontal plane including a bottommost surface of the second alternating stack.Type: ApplicationFiled: May 18, 2020Publication date: November 18, 2021Inventors: Kengo KAJIWARA, Atsushi SHIMODA, Tatsuya HINOUE, Junpei KANAZAWA, Masanori TERAHARA
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Publication number: 20210358936Abstract: A alternating stack of insulating layers and sacrificial material layers is formed over a substrate. An array of memory opening fill structures and an array of support pillar structures are formed through the alternating stack. Backside trenches are formed through the alternating stack by performing an anisotropic etch process. The anisotropic etch process etches peripheral portions of a subset of the array of support pillar structures. The sacrificial material layers are replaced with electrically conductive layer by forming backside recesses while the support pillar structures provide mechanical support to the insulating layers.Type: ApplicationFiled: September 29, 2020Publication date: November 18, 2021Inventors: Shunsuke TAKUMA, Seiji SHIMABUKURO, Kengo KAJIWARA
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Patent number: 11018152Abstract: First memory openings are formed through a first alternating stack of first insulating layers and first spacer material layers. Each first memory opening is filled with a first memory film, a sacrificial dielectric liner, and a first-tier opening fill material portion. Second memory openings are formed through a second alternating stack of second insulating layers and second spacer material layers. A second memory film is formed in each second memory opening. The first-tier opening fill material portions are removed selective to the sacrificial dielectric liners. The sacrificial dielectric liners are removed selective to the second memory films and the first memory films. A vertical semiconductor channel can be formed on each vertical stack of a first memory film and a second memory film.Type: GrantFiled: July 5, 2019Date of Patent: May 25, 2021Assignee: SANDISK TECHNOLOGIES LLCInventors: Tatsuya Hinoue, Kengo Kajiwara, Ryousuke Itou, Naohiro Hosoda
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Publication number: 20210005627Abstract: First memory openings are formed through a first alternating stack of first insulating layers and first spacer material layers. Each first memory opening is filled with a first memory film, a sacrificial dielectric liner, and a first-tier opening fill material portion. Second memory openings are formed through a second alternating stack of second insulating layers and second spacer material layers. A second memory film is formed in each second memory opening. The first-tier opening fill material portions are removed selective to the sacrificial dielectric liners. The sacrificial dielectric liners are removed selective to the second memory films and the first memory films. A vertical semiconductor channel can be formed on each vertical stack of a first memory film and a second memory film.Type: ApplicationFiled: July 5, 2019Publication date: January 7, 2021Inventors: Tatsuya HINOUE, Kengo KAJIWARA, Ryosuke ITOU, Naohiro HOSODA, Yohei MASAMORI, Kota FUNAYAMA, Keisuke TSUKAMOTO, Hirofumi WATATANI
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Patent number: 10804197Abstract: A three-dimensional memory device includes a pair of alternating stacks of insulating layers and electrically conductive layers located over a semiconductor region, and laterally spaced from each other by a backside trench, memory stack structures extending through the pair of alternating, each memory stack structure containing a vertical semiconductor channel and a memory film, and a backside contact assembly located in the backside trench. The backside contact assembly includes an isolation dielectric spacer contacting the pair of alternating stacks, a conductive liner contacting inner sidewalls of the isolation dielectric spacer and a top surface of the semiconductor region, and composite non-metallic core containing at least one outer dielectric fill material portion that is laterally enclosed by a lower portion of the conductive liner and a dielectric core contacting an inner sidewall of the at least one outer dielectric fill material portion.Type: GrantFiled: July 19, 2019Date of Patent: October 13, 2020Assignee: SANDISK TECHNOLOGIES LLCInventors: Motoki Kawasaki, Arata Okuyama, Xun Gu, Kengo Kajiwara, Jixin Yu
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Publication number: 20200312765Abstract: A three-dimensional memory device includes a pair of alternating stacks of insulating layers and electrically conductive layers located over a semiconductor region, and laterally spaced from each other by a backside trench, memory stack structures extending through the pair of alternating, each memory stack structure containing a vertical semiconductor channel and a memory film, and a backside contact assembly located in the backside trench. The backside contact assembly includes an isolation dielectric spacer contacting the pair of alternating stacks, a conductive liner contacting inner sidewalls of the isolation dielectric spacer and a top surface of the semiconductor region, and composite non-metallic core containing at least one outer dielectric fill material portion that is laterally enclosed by a lower portion of the conductive liner and a dielectric core contacting an inner sidewall of the at least one outer dielectric fill material portion.Type: ApplicationFiled: July 19, 2019Publication date: October 1, 2020Inventors: Motoki KAWASAKI, Arata OKUYAMA, Xun GU, Kengo KAJIWARA, Jixin YU
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Patent number: 9991277Abstract: A memory opening can be formed through an alternating stack of insulating layers and sacrificial material layers over a substrate. A material layer stack containing, from outside to inside, an aluminum oxide tunneling dielectric layer, a silicon-containing tunneling dielectric layer, and a vertical semiconductor channel is formed within the memory opening. After forming backside recesses by removing the sacrificial material layers, charge trapping material portions are formed on physically exposed surfaces of the aluminum oxide tunneling dielectric layer by employing a selective silicon nitride deposition process. A backside blocking dielectric layer and electrically conductive layers are formed in the backside recesses. The charge trapping material portions are discrete silicon nitride portions located at levels of the electrically conductive layers and vertically spaced from one another by the insulating layers.Type: GrantFiled: November 28, 2016Date of Patent: June 5, 2018Assignee: SANDISK TECHNOLOGIES LLCInventors: Masanori Tsutsumi, Kengo Kajiwara, Raghuveer S. Makala
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Publication number: 20180151588Abstract: A memory opening can be formed through an alternating stack of insulating layers and sacrificial material layers over a substrate. A material layer stack containing, from outside to inside, an aluminum oxide tunneling dielectric layer, a silicon-containing tunneling dielectric layer, and a vertical semiconductor channel is formed within the memory opening. After forming backside recesses by removing the sacrificial material layers, charge trapping material portions are formed on physically exposed surfaces of the aluminum oxide tunneling dielectric layer by employing a selective silicon nitride deposition process. A backside blocking dielectric layer and electrically conductive layers are formed in the backside recesses. The charge trapping material portions are discrete silicon nitride portions located at levels of the electrically conductive layers and vertically spaced from one another by the insulating layers.Type: ApplicationFiled: November 28, 2016Publication date: May 31, 2018Inventors: Masanori Tsutsumi, Kengo Kajiwara, Raghuveer S. Makala
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Patent number: 9754999Abstract: A method is provided that includes forming a transistor by forming a gate disposed in a first direction above a substrate, the gate including a first bridge portion and a second bridge portion, forming the first bridge portion extending in the first direction and disposed near a top of the gate, and forming the second bridge portion extending in the first direction and disposed near a bottom of the gate.Type: GrantFiled: August 18, 2016Date of Patent: September 5, 2017Assignee: SanDisk Technologies LLCInventors: Seje Takaki, Manabu Hayashi, Ryousuke Itou, Takuro Maede, Kengo Kajiwara, Tetsuya Yamada, Yusuke Oda
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Patent number: 9673257Abstract: A method is provided that includes forming a transistor by forming a first a rail gate disposed in a first direction above a substrate, forming a second rail gate disposed in a second direction above the substrate, the second direction perpendicular to the first direction, and forming a bridge section disposed between the first rail gate and the second rail gate.Type: GrantFiled: June 3, 2016Date of Patent: June 6, 2017Assignee: SanDisk Technologies LLCInventors: Seje Takaki, Manabu Hayashi, Akira Nakada, Ryousuke Itou, Takuro Maede, Kengo Kajiwara, Tetsuya Yamada
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Patent number: 9589839Abstract: Corner rounding of electrically conductive layers in a replacement electrode integration scheme can be alleviated by employing compositionally modulated sacrificial material layers. An alternating stack of insulating layers and compositionally modulated sacrificial material layers can be formed over a substrate. Each of the compositionally modulated sacrificial material layers has a vertical modulation of material composition such that each compositionally modulated sacrificial material layer provides greater resistance to conversion into a silicon-oxide-containing material at upper and lower portions thereof than at a middle portion thereof during a subsequent oxidation process. Bird's beak features can be formed with lesser dimensions, and electrically conductive layers formed by replacement of remaining portions of the sacrificial material layers with a conductive material can have less corner rounding.Type: GrantFiled: February 1, 2016Date of Patent: March 7, 2017Assignee: SANDISK TECHNOLOGIES LLCInventors: Yusuke Ikawa, Kiyohiko Sakakibara, Eisuke Takii, Kengo Kajiwara, Seiji Shimabukuro, Akira Matsudaira, Hiroyuki Ogawa