Abstract: A semiconductor integrated circuit includes: a memory collars including: a memory cell; a fetch register that is configured to fetch data as a first fetch data; a comparing unit that is configured to compare the first fetch data with an expected value; a failure detecting signal output unit that is configured to receive the compared result and output a failure detecting signal; and a BIST circuit including: a BIST control unit that is configured to output an instruction and output a BIST status; a shift controller that is configured to receive a first clock signal, the BIST status signal, and the failure detecting signal and output sift enable signal; a shift counter that counts the number of clock pulses on the first clock signal; a first storage register that is configured to receive the first clock signal and the shift enable signal, and a second storage register that is configured to receive a second clock signal.

Abstract: A semiconductor integrated circuit has a memory collar including a memory cell configured to store a written data pattern and read and output the data pattern, and a register configured to store a failed data pattern, and a built-in self test circuit configured to write the data pattern in the memory cell, output expected value data, and decide whether to continue a test or suspend the test to output failure information to outside, based on a comparison result of the data pattern outputted from the memory cell and the expected value data and a comparison result of the data pattern and the failed data pattern.

Abstract: According to one embodiment, an electrical package includes: an external input portion; an external output portion; a plurality of integrated circuits that is compatible with a compressed deterministic pattern test, each of the integrated circuits including: an input portion; a decompressor that is connected to the input portion; scan chains that are connected to the decompressor; a compactor that is connected to the scan chains; a selector that is connected to the compactor and the input portion to selectively output an output of the compactor or an output of the input portion; and an output portion that is connected to the selector.

Abstract: An integrated circuit device according to an embodiment of this invention includes: a memory having: a first port to which a first clock signal is input, and a second port to which a second clock signal is input; and a built-in self test circuit having: a first signal generating circuit to which the first clock signal is input, a second signal generating circuit to which the second clock signal is input, a clock selecting circuit to which the first and second clock signals are input and which selects and outputs one of the input clock signals, and a controlling circuit which outputs a clock requesting signal requesting one of the first and second clock signals to the clock selecting circuit, operates in accordance with the clock signal selected and output by the clock selecting circuit, and outputs a controlling signal for controlling one of the first and second signal generating circuits.

Abstract: According to the present invention, there is provided a semiconductor integrated circuit having: a BIST circuit including, a data generator which generates and outputs write data to be supplied to a memory, an address generator which generates and outputs an address signal to be supplied to the memory, a control signal generator which generates and outputs a control signal for controlling the memory, a result analyzer which receives a flag signal, analyzes a result of a BIST, and outputs a BIST result signal, a BIST controller which controls operations of the data generator, the address generator, the control signal generator, and the result analyzer, and outputs a BIST state signal indicating a state of the BIST, and a diagnostic data storage circuit including a first capture register which captures and outputs, in accordance with a first clock, a latest address signal and the BIST state signal output from the BIST controller while no flag signal is supplied, and maintains outputs when the flag signal is sup

Abstract: According to the present invention, there is provided a semiconductor integrated circuit comprising: a logic circuit which operates upon receiving a clock; a logic built-in self test circuit which executes a built-in self test of said logic circuit, said logic built-in self test circuit having a pattern generator which generates a pattern to be input to said logic circuit, a pattern compactor which receives data output from said logic circuit that has received the pattern, compacts the data, and outputs a result, and a logic built-in self test control unit which controls operations of said pattern generator and said pattern compactor and controls an operation of causing a scan path in said logic circuit to shift upon receiving the pattern; a device circuit which operates upon receiving the clock; and a device circuit built-in self test circuit which executes a built-in self test of said device circuit, wherein while said device circuit built-in self test circuit is executing the built-in self test of said dev

Abstract: A semiconductor integrated circuit includes: a logic circuit to be tested; a memory connected the logic circuit to be tested; a BIST circuit for testing the memory; and a bypass circuit connected between the memory and the logic circuit and between the memory and the BIST circuit, the bypass circuit has a parallel test path for testing the logic circuit and the memory in parallel, and a signal line test path for testing non-tested signal lines in the parallel test path, and the bypass circuit selectively switches the parallel test path and the signal line test path.

Abstract: An aspect of the present invention provides a semiconductor integrated circuit verification system that includes a compiler configured to receive circuit descriptions of a semiconductor integrated circuit to be verified and create a circuit database, a circuit analysis unit configured to receive the circuit database to analyze the circuitry inside the semiconductor integrated circuit based on the circuit database, the circuit analysis unit configured to determine the timing at which the abstraction level of the circuit is switched and generate a simulation object, and a simulation execution unit configured to receive the simulation object and conduct a simulation of the semiconductor integrated circuit based on the simulation object.

Abstract: A built-in self test circuit includes a capture register storing data transmitted from a memory device, an operation controller controlling operation of the memory device and the capture register, a hold controller executing a hold operation to stop a read operation and a write operation of the memory device by transmitting a hold signal to the operation controller, and a test control circuit controlling the operation controller to transmit a capture signal so that the capture register stores the data to the capture register.

Abstract: A semiconductor integrated circuit includes a plurality of memories; a BIST circuit configured to test at least one of the memories; and a plurality of shift circuits connected to each of the memories, each of the shift circuits shifts one of first data bits obtained from at least one of the memories and a second data bits having a smaller number of bits than the first data bits, in synchronization with an external clock, by electing one of the first and second data bits in accordance with a swiching signal from the BIST circuit; wherein the shift circuits are connected to one another so as to form a part of a serial shift path.

Abstract: A method for generating a test vector of an IC including: designating a retrieval condition to select a path on which a signal can be transmitted in the circuit; executing a timing analysis of the circuit based on a circuit information of the circuit, retrieving the path satisfying the retrieval condition, and generating a path list in which cells composing the retrieved path are put in order of executing the timing analysis; generating a test vector to test a path delay fault of the circuit based on the path list; designating an ending condition to end generation of the test vector when the path in the path list for the test vector is distributed over the circuit; and stopping generation of the path list when the ending condition is satisfied.

Abstract: A semiconductor integrated circuit includes a self-testing circuit having a test circuit which is incorporated in a logic circuit to test the logic circuit. The test circuit has a test pattern generator to generate a test pattern and a compressor to compress a test result output. The logic circuit includes a plurality of scan chains including a plurality of serial connected registers and the compressor includes a through output portion. The semiconductor integrated circuit also includes a pattern counter which counts the test pattern at a test time of the logic circuit, a shift counter which counts the number of shifts in the scan chain in the logic circuit at the test time, and a failure information output circuit which is connected to the test circuit and which outputs step information of the test pattern corresponding to a failure to an integrated circuit external terminal when the failure is detected at the test time.

Abstract: A built-in self test circuit includes a capture register storing data transmitted from a memory device, an operation controller controlling operation of the memory device and the capture register, a hold controller executing a hold operation to stop a read operation and a write operation of the memory device by transmitting a hold signal to the operation controller, and a test control circuit controlling the operation controller to transmit a capture signal so that the capture register stores the data to the capture register.

Abstract: A semiconductor integrated circuit includes: a logic circuit to be tested; a memory connected the logic circuit to be tested; a BIST circuit for testing the memory; and a bypass circuit connected between the memory and the logic circuit and between the memory and the BIST circuit, the bypass circuit has a parallel test path for testing the logic circuit and the memory in parallel, and a signal line test path for testing non-tested signal lines in the parallel test path, and the bypass circuit selectively switches the parallel test path and the signal line test path.

Abstract: An aspect of the present invention provides a semiconductor integrated circuit verification system that includes a compiler configured to receive circuit descriptions of a semiconductor integrated circuit to be verified and create a circuit database, a circuit analysis unit configured to receive the circuit database to analyze the circuitry inside the semiconductor integrated circuit based on the circuit database, the circuit analysis unit configured to determine the timing at which the abstraction level of the circuit is switched and generate a simulation object, and a simulation execution unit configured to receive the simulation object and conduct a simulation of the semiconductor integrated circuit based on the simulation object.

Abstract: A method for generating a test vector of a semiconductor integrated circuit including: designating a retrieval condition to select a path on which a signal can be transmitted in the circuit; executing a timing analysis of the circuit based on a circuit information of the circuit, retrieving the path satisfying the retrieval condition, and generating a path list in which cells composing the retrieved path are put in order of executing the timing analysis; generating a test vector to test a path delay fault of the circuit based on the path list; designating an ending condition to end generation of the test vector when the path in the path list for the test vector is distributed over the circuit; and stopping generation of the path list when the ending condition is satisfied.

Abstract: An integrated includes a test pattern generation unit, which divides a test pattern into scanning test patterns; scan chains, which shift in the scanning test patterns, output them to a logic circuit at the same time, input the test results from the logic circuit, and shift out them; and a test result compression unit, which is connected to the output stages of the scan chains, compresses the test results into the same number of compressed test result signatures as the test results, and outputs them to the scan chains in a first order that allows one-to-one mapping.

Abstract: There is disclosed a semiconductor integrated circuit comprising a logic BIST circuit which includes a test pattern generator and test result compressor and which performs a built-in self test (logic BIST) of a logic circuit, a pattern counter which counts test patterns during the logic BIST, an expected value comparison circuit which compares a compressed value output of the test result compressor with an expected value input from an external tester for each test pattern and which outputs a failure flag at a mismatch detection time, an external terminal which outputs the failure flag from the LSI, and an external terminal which outputs from the LSI a pattern count signal at a time when the pattern counter receives the failure flag.