Patents by Inventor Kenichi Arakawa

Kenichi Arakawa has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20240382881
    Abstract: This supply air demister comprises a duct forming a flow channel through which supply air flows upward from below, and a demister body provided above the duct. The demister body has: a plurality of gutter parts having a receiving surface depressed downward and extending obliquely, and provided side by side at intervals from each other; and a plurality of return parts provided above the gutter parts, having a return surface depressed upward, and provided side by side at intervals from each other. The return parts are configured such that a return surface overlaps with an adjacent receiving surface in the extending direction of the return surface as viewed in the vertical direction.
    Type: Application
    Filed: February 14, 2022
    Publication date: November 21, 2024
    Applicant: MITSUBISHI HEAVY INDUSTRIES, LTD.
    Inventors: Yoshiaki ARAKAWA, Takashi IKEDA, Kenichi IWANAGA, Go TOMATSU, Koji IWASAKI
  • Patent number: 12027217
    Abstract: A semiconductor device and an operation method capable of operating with high reliability are provided. A voltage monitoring circuit (100) of the disclosure includes: a power-on detection part (110) configurated to detect whether a supply voltage (EXVDD) of an external power supply terminal has reached a power-on voltage level; a timer (120) configurated to measure a predetermined time when the power-on voltage level is detected; a through current generation part (130) configurated to generate a through current between the external power supply terminal and GND during a period when the timer (120) measures the predetermined time; and a power-off detection part (140) configurated to detect whether a drop of the supply voltage (EXVDD) has reached a power-off voltage level when the through current is generated.
    Type: Grant
    Filed: April 20, 2022
    Date of Patent: July 2, 2024
    Assignee: Winbond Electronics Corp.
    Inventor: Kenichi Arakawa
  • Publication number: 20230188871
    Abstract: The present technology relates to a solid-state imaging device, a driving method, and an electronic device capable of suppressing leakage of charge from PD to FD. In a solid-state imaging device according to an aspect of the present technology, in a case where the charge is read out from a selected photoelectric conversion unit as a charge readout target out of the plurality of photoelectric conversion units sharing the shared holding unit to the shared holding unit, a drive control unit applies a first pulse to the readout unit that corresponds to the selected photoelectric conversion unit, and applies a second pulse having a polarity opposite to a polarity of the first pulse and having a pulse period overlapping with at least a portion of the pulse period of the first pulse, to a site coming into a capacitive coupling state with the shared holding unit. The present technology is applicable to a back-illumination CMOS image sensor, for example.
    Type: Application
    Filed: November 21, 2017
    Publication date: June 15, 2023
    Inventors: KENICHI ARAKAWA, HIROKI UI
  • Patent number: 11502680
    Abstract: A power down detection circuit and a semiconductor storage apparatus, which can adjust a power down detection level while suppressing temperature dependence, are provided. The power down detection circuit includes a BGR circuit, a trimming circuit, a resistance division circuit, and a comparator. The BGR circuit generates a reference voltage based on a supply voltage. The trimming circuit adjusts the reference voltage based on a trimming signal to generate a reference voltage for power down detection. The resistance division circuit generates an internal voltage lower than the supply voltage. The comparator detects that the internal voltage is lower than the reference voltage for power down detection and outputs a reset signal.
    Type: Grant
    Filed: April 22, 2021
    Date of Patent: November 15, 2022
    Assignee: Winbond Electronics Corp.
    Inventor: Kenichi Arakawa
  • Publication number: 20220359018
    Abstract: A semiconductor device and an operation method capable of operating with high reliability are provided. A voltage monitoring circuit (100) of the disclosure includes: a power-on detection part (110) configurated to detect whether a supply voltage (EXVDD) of an external power supply terminal has reached a power-on voltage level; a timer (120) configurated to measure a predetermined time when the power-on voltage level is detected; a through current generation part (130) configurated to generate a through current between the external power supply terminal and GND during a period when the timer (120) measures the predetermined time; and a power-off detection part (140) configurated to detect whether a drop of the supply voltage (EXVDD) has reached a power-off voltage level when the through current is generated.
    Type: Application
    Filed: April 20, 2022
    Publication date: November 10, 2022
    Applicant: Winbond Electronics Corp.
    Inventor: Kenichi Arakawa
  • Patent number: 11227658
    Abstract: A flash memory having high reliability and a method for controlling the flash memory is provided for seeking stability of memory cell threshold voltage distribution. A NAND string of the flash memory has: a source-line-side select transistor; a source-line-side dummy cell; a plurality of memory cells; a bit-line-side dummy cell; and a bit-line-side select transistor. A method for controlling the flash memory includes the following step: after erasing a selected block, programming the dummy cell of the selected block into a programmed state by applying a programming voltage to a dummy word line which is connected to the dummy cell.
    Type: Grant
    Filed: June 17, 2020
    Date of Patent: January 18, 2022
    Assignee: WINBOND ELECTRONICS CORP.
    Inventors: Kenichi Arakawa, Sho Okabe
  • Publication number: 20210351771
    Abstract: A power down detection circuit and a semiconductor storage apparatus, which can adjust a power down detection level while suppressing temperature dependence, are provided. The power down detection circuit includes a BGR circuit, a trimming circuit, a resistance division circuit, and a comparator. The BGR circuit generates a reference voltage based on a supply voltage. The trimming circuit adjusts the reference voltage based on a trimming signal to generate a reference voltage for power down detection. The resistance division circuit generates an internal voltage lower than the supply voltage. The comparator detects that the internal voltage is lower than the reference voltage for power down detection and outputs a reset signal.
    Type: Application
    Filed: April 22, 2021
    Publication date: November 11, 2021
    Applicant: Winbond Electronics Corp.
    Inventor: Kenichi Arakawa
  • Publication number: 20200402583
    Abstract: A flash memory having high reliability and a method for controlling the flash memory is provided for seeking stability of memory cell threshold voltage distribution. A NAND string of the flash memory has: a source-line-side select transistor; a source-line-side dummy cell; a plurality of memory cells; a bit-line-side dummy cell; and a bit-line-side select transistor. A method for controlling the flash memory includes the following step: after erasing a selected block, programming the dummy cell of the selected block into a programmed state by applying a programming voltage to a dummy word line which is connected to the dummy cell.
    Type: Application
    Filed: June 17, 2020
    Publication date: December 24, 2020
    Applicant: Winbond Electronics Corp.
    Inventors: Kenichi ARAKAWA, Sho OKABE
  • Patent number: 10672485
    Abstract: A semiconductor storage device achieving stabilization of an operating voltage of a selected memory chip. A flash memory device of the disclosure includes a master chip and at least one slave chip. A voltage output portion of a charge pump circuit of the master chip is connected to an internal pad of the master chip, and a voltage output portion of a charge pump circuit of the slave chip is connected to an internal pad of the slave chip, the internal pad of the master chip and the internal pad of the slave chip are connected by a wire. When the mater chip is operated, the charge pump circuit of the master chip is turned off, the charge pump circuit of the slave chip is turned on, and a voltage generated by the charge pump circuit of the slave chip is supplied to the master chip.
    Type: Grant
    Filed: January 10, 2019
    Date of Patent: June 2, 2020
    Assignee: Winbond Electronics Corp.
    Inventor: Kenichi Arakawa
  • Patent number: 10497448
    Abstract: A semiconductor memory device facilitating an area efficiency of a page buffer/sense circuit and suppressing erroneous operation due to capacitive coupling between wires is provided. The flash memory 100 of the disclosure includes a memory cell array 110 and a page buffer/sense circuit 170. The memory cell array 110 includes a plurality of memory cells. The page buffer/sense circuit 170 holds data read from a page selected by the memory cell array 110 or holds data to be programmed to a page selected by the memory cell array 110. The page buffer/sense circuit 170 is arranged in n columns×m segments within one pitch in a row direction defined by p number of bit lines extending from the memory cell array 110. n is an integer of 2 or more then 2, and m is an integer of 2 or more then 2.
    Type: Grant
    Filed: August 23, 2018
    Date of Patent: December 3, 2019
    Assignee: Winbond Electronics Corp.
    Inventor: Kenichi Arakawa
  • Publication number: 20190214098
    Abstract: A semiconductor storage device achieving stabilization of an operating voltage of a selected memory chip. A flash memory device of the disclosure includes a master chip and at least one slave chip. A voltage output portion of a charge pump circuit of the master chip is connected to an internal pad of the master chip, and a voltage output portion of a charge pump circuit of the slave chip is connected to an internal pad of the slave chip, the internal pad of the master chip and the internal pad of the slave chip are connected by a wire. When the mater chip is operated, the charge pump circuit of the master chip is turned off, the charge pump circuit of the slave chip is turned on, and a voltage generated by the charge pump circuit of the slave chip is supplied to the master chip.
    Type: Application
    Filed: January 10, 2019
    Publication date: July 11, 2019
    Applicant: Winbond Electronics Corp.
    Inventor: Kenichi Arakawa
  • Publication number: 20190115084
    Abstract: A semiconductor memory device facilitating an area efficiency of a page buffer/sense circuit and suppressing erroneous operation due to capacitive coupling between wires is provided. The flash memory 100 of the disclosure includes a memory cell array 110 and a page buffer/sense circuit 170. The memory cell array 110 includes a plurality of memory cells. The page buffer/sense circuit 170 holds data read from a page selected by the memory cell array 110 or holds data to be programmed to a page selected by the memory cell array 110. The page buffer/sense circuit 170 is arranged in n columns×m segments within one pitch in a row direction defined by p number of bit lines extending from the memory cell array 110. n is an integer of 2 or more then 2, and m is an integer of 2 or more then 2.
    Type: Application
    Filed: August 23, 2018
    Publication date: April 18, 2019
    Applicant: Winbond Electronics Corp.
    Inventor: Kenichi Arakawa
  • Patent number: 9865358
    Abstract: Provided is a flash memory device capable of restricting power consumption in an erase operation. The invention includes a plurality of wells, a power supply device, and a coupling device. The power supply device applies erase voltages to the wells for performing an erase operation. The coupling device performs selective coupling between the wells. When performing the erase operation on the wells, the power supply device applies the erase voltage to one of the wells, and applies the erase voltage to the other one of the wells after the coupling device electrically couples the one of the wells to the other one of the wells.
    Type: Grant
    Filed: February 17, 2017
    Date of Patent: January 9, 2018
    Assignee: Windbond Electronics Corp.
    Inventors: Hiroki Murakami, Kenichi Arakawa
  • Publication number: 20170243656
    Abstract: Provided is a flash memory device capable of restricting power consumption in an erase operation. The invention includes a plurality of wells, a power supply device, and a coupling device. The power supply device applies erase voltages to the wells for performing an erase operation. The coupling device performs selective coupling between the wells. When performing the erase operation on the wells, the power supply device applies the erase voltage to one of the wells, and applies the erase voltage to the other one of the wells after the coupling device electrically couples the one of the wells to the other one of the wells.
    Type: Application
    Filed: February 17, 2017
    Publication date: August 24, 2017
    Inventors: Hiroki MURAKAMI, Kenichi ARAKAWA
  • Patent number: 9724683
    Abstract: Provided is a catalyst structure which prevents an increase in pressure loss by a simple construction while the gas flow is efficiently stirred by a structure making contact between adjacent catalyst elements. The catalyst structure is provided with a first flat-plate part and a second flat-plate part which support, on surfaces thereof, a constituent having catalytic activity to an exhaust gas and face each other, and a stirring part which is provided in such a manner as to come into contact first with the first flat-plate part and the second flat-plate part in an extending manner from the first flat-plate part to the second flat-plate part at a prescribed angle with respect to the direction in which the exhaust gas flows.
    Type: Grant
    Filed: July 11, 2013
    Date of Patent: August 8, 2017
    Assignee: MITSUBISHI HITACHI POWER SYSTEMS, LTD.
    Inventors: Yasuyoshi Kato, Keiichiro Kai, Kenichi Arakawa, Naomi Imada
  • Publication number: 20160276397
    Abstract: A solid-state imaging device according to an embodiment includes a first semiconductor layer of a first conductivity type, a photodiode region in which a second semiconductor layer of a second conductivity type is formed in a surface of the first semiconductor layer, a first interlayer insulating film which is formed on the first semiconductor layer and on the photodiode region, a first fixed charge film which is formed on the first interlayer insulating film and has a charge of the second conductivity type, a second interlayer insulating film which is formed on or above the first fixed charge film, and a second fixed charge film which is formed on the second interlayer insulating film and has a charge of the second conductivity type.
    Type: Application
    Filed: September 3, 2015
    Publication date: September 22, 2016
    Applicant: Kabushiki Kaisha Toshiba
    Inventor: Kenichi ARAKAWA
  • Patent number: 9396803
    Abstract: A semiconductor memory device, which restrains a breakdown of a low-voltage transistor constructing a bit line selecting circuit, is provided. An NAND string unit and transistors (BLSe, BLso, BIASe, BIASo) that construct bit line selecting circuit are formed in a P-well. The transistors are set in a floating state during erasing operation. The voltages of the transistors are increased when an erasing voltage is applied to the P-well. When the erasing voltage is discharged from the P-well, the gates of the transistors are connected to a reference potential via a discharging circuit (410) such that the gate voltage follows the voltage of the P-well to be discharged.
    Type: Grant
    Filed: June 16, 2015
    Date of Patent: July 19, 2016
    Assignee: Winbond Electronics Corp.
    Inventor: Kenichi Arakawa
  • Publication number: 20160141039
    Abstract: A semiconductor memory device, which restrains a breakdown of a low-voltage transistor constructing a bit line selecting circuit, is provided. An NAND string unit and transistors (BLSe, BLso, BIASe, BIASo) that construct bit line selecting circuit are formed in a P-well. The transistors are set in a floating state during erasing operation. The voltages of the transistors are increased when an erasing voltage is applied to the P-well. When the erasing voltage is discharged from the P-well, the gates of the transistors are connected to a reference potential via a discharging circuit (410) such that the gate voltage follows the voltage of the P-well to be discharged.
    Type: Application
    Filed: June 16, 2015
    Publication date: May 19, 2016
    Inventor: Kenichi Arakawa
  • Patent number: 9263145
    Abstract: The invention provides a current detection circuit and a semiconductor memory apparatus using the current detection circuit thereof. The current detection circuit is capable of rapidly sensing the current flowing through a tiny bit line structure. A page buffer/sensing circuit of the invention includes: a transistor TP3 pre-charging a node SNS during a pre-charge period and providing a target constant current to the node SNS during a discharge period; a transistor TN3 pre-charging the bit line according to the voltage pre-charged to the node SNS; and a transistor TP2 connected to the node SNS. The transistor TP2 detects whether or not a current larger than the constant current supplied by the transistor TP3 is discharged from the bit line and outputs a detection result to a node SENSE.
    Type: Grant
    Filed: November 10, 2014
    Date of Patent: February 16, 2016
    Assignee: WINBOND ELECTRONICS CORP.
    Inventor: Kenichi Arakawa
  • Patent number: 9153335
    Abstract: The invention provides a clamp voltage generating circuit capable of generating a correct clamp voltage. The clamp voltage generating circuit includes an emulate transistor, having a drain coupled to a power source VDD, a source coupled to a node, and a gate coupled to the clamp voltage; a current setting circuit, connected between the node and ground, for setting a current flowing from the node to the ground; a regulator, inputting a feedback voltage from the node and a reference voltage, and outputting a voltage VCLMP. The current setting circuit duplicates a current of a bit line, so that the emulate transistor is similar to a charge transfer transistor.
    Type: Grant
    Filed: June 11, 2014
    Date of Patent: October 6, 2015
    Assignee: Winbond Electronics Corp.
    Inventors: Hiroki Murakami, Kenichi Arakawa