Patents by Inventor Kenichi Kawakami

Kenichi Kawakami has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20210114712
    Abstract: The method for producing an assembly is a method for producing an assembly equipped with a member to be reinforced (20), a reinforcing member body (41), and a filler (42), wherein the reinforcing member body (41) has a pair of flanges (44) arranged spaced on the surface (20B) of the member to be reinforced (20), a web (45), and a connection portion (46) which connects the flanges (44) and the web (45) and forms a filler space (V) with the surface (20B). The method for producing an assembly includes a step for inserting a filler (42) into the filler space (V), a step for attaching a crack control member (43) to cover the end of the filler (42), a step for joining the flanges (44) and the member to be reinforced (20), and a step for curing at least the member to be reinforced (20).
    Type: Application
    Filed: November 26, 2018
    Publication date: April 22, 2021
    Inventors: Akihito SUZUKI, Kenji MURAKAMI, Kana SAKON, Akihisa OKUDA, Takayuki SHIMIZU, Takumi SHINOHARA, Jun ETO, Yukifumi TOYAMA, Junichiro MIYAGAKI, Kenichi KAWAKAMI
  • Patent number: 8487648
    Abstract: A semiconductor integrated circuit includes a macro connected between a first power supply line and a second power supply line to drive a load, and a power-supply-noise cancelling circuit connected between an input and an output of the macro to generate a current for canceling one of a current flowing from the first power supply line to the output of the macro and a current flowing from the output of the macro to the second power supply line, on the basis of a potential difference between the input and the output of the macro. The macro and the power-supply-noise cancelling circuit are mounted in a same chip.
    Type: Grant
    Filed: June 16, 2011
    Date of Patent: July 16, 2013
    Assignee: Renesas Electronics Corporation
    Inventors: Masashi Kurokawa, Kenichi Kawakami
  • Patent number: 8384480
    Abstract: A differential amplifier includes first and second current paths, each connected between first and second power supplies (PS) and respectively outputting first and second differential output signals. The first current path includes: first transistor, selectively interconnected between the first PS and a first output terminal, its gate receiving one differential input signal; second transistor, connected between the second PS and the first output terminal, its gate receiving the other differential input signal; and first switch circuit. The second current path includes: third transistor, selectively interconnected between the second PS and a second output terminal, its gate receiving one differential input signal; fourth transistor, connected between the first PS and the second output terminal, its gate receiving the other differential input signal; and second switch circuit. One of the first and second switch circuits is connected to the first PS and the other is connected to the second PS.
    Type: Grant
    Filed: September 24, 2011
    Date of Patent: February 26, 2013
    Assignee: Renesas Electronics Corporation
    Inventors: Michimasa Yamaguchi, Kenichi Kawakami
  • Publication number: 20120126894
    Abstract: A differential amplifier includes first and second current paths, each connected between first and second power supplies (PS) and respectively outputting first and second differential output signals. The first current path includes: first transistor, selectively interconnected between the first PS and a first output terminal, its gate receiving one differential input signal; second transistor, connected between the second PS and the first output terminal, its gate receiving the other differential input signal; and first switch circuit. The second current path includes: third transistor, selectively interconnected between the second PS and a second output terminal, its gate receiving one differential input signal; fourth transistor, connected between the first PS and the second output terminal, its gate receiving the other differential input signal; and second switch circuit. One of the first and second switch circuits is connected to the first PS and the other is connected to the second PS.
    Type: Application
    Filed: September 24, 2011
    Publication date: May 24, 2012
    Applicant: RENESAS ELECTRONICS CORPORATION
    Inventors: Michimasa YAMAGUCHI, Kenichi KAWAKAMI
  • Patent number: 8125274
    Abstract: A differential amplifier including: 1st transistor that is connected between 1st power-supply terminal and 1st output terminal, and has a control terminal receiving one of the differential input signals; 2nd transistor that is connected between 2nd power-supply terminal and 1st output terminal, and has a control terminal receiving the other of the differential input signals; 1st switch that is connected between 1st power-supply terminal and 1st transistor; 3rd transistor that is connected between 2nd power-supply terminal and 2nd output terminal, and has a control terminal receiving one of the differential input signals; 4th transistor that is connected between 1st power-supply terminal and 2nd output terminal, and has a control terminal receiving the other of the differential input signals; 2nd switch that is connected between 2nd power-supply terminal and 3rd transistor. Drive state of 1st and 2nd switches are controlled by a control signal.
    Type: Grant
    Filed: June 2, 2010
    Date of Patent: February 28, 2012
    Assignee: Renesas Electronics Corporation
    Inventors: Michimasa Yamaguchi, Kenichi Kawakami
  • Publication number: 20110248741
    Abstract: A semiconductor integrated circuit includes a macro connected between a first power supply line and a second power supply line to drive a load, and a power-supply-noise cancelling circuit connected between an input and an output of the macro to generate a current for canceling one of a current flowing from the first power supply line to the output of the macro and a current flowing from the output of the macro to the second power supply line, on the basis of a potential difference between the input and the output of the macro. The macro and the power-supply-noise cancelling circuit are mounted in a same chip.
    Type: Application
    Filed: June 16, 2011
    Publication date: October 13, 2011
    Applicant: Renesas Electronics Corporation
    Inventors: Masashi Kurokawa, Kenichi Kawakami
  • Patent number: 7982490
    Abstract: Provided is a semiconductor integrated circuit including: an output circuit connected between a power supply (VDD0) and a ground (GND0), having an input connected to an input terminal, and having an output connected to an output terminal; and a power-supply-noise cancelling circuit connected between the input terminal and the output terminal to generate a current that cancels a current flowing from the power supply (VDD0) to the output terminal or a current flowing from the output terminal to the ground (GND0), based on a potential difference between the input terminal and the output terminal.
    Type: Grant
    Filed: March 23, 2009
    Date of Patent: July 19, 2011
    Assignee: Renesas Electronics Corporation
    Inventors: Masashi Kurokawa, Kenichi Kawakami
  • Publication number: 20110025416
    Abstract: A differential amplifier including: 1st transistor that is connected between 1st power-supply terminal and 1st output terminal, and has a control terminal receiving one of the differential input signals; 2nd transistor that is connected between 2nd power-supply terminal and 1st output terminal, and has a control terminal receiving the other of the differential input signals; 1st switch that is connected between 1st power-supply terminal and 1st transistor; 3rd transistor that is connected between 2nd power-supply terminal and 2nd output terminal, and has a control terminal is input to one of the differential input signals; 4th transistor that is connected between 1st power-supply terminal and 2nd output terminal, and has a control terminal receiving the other of the differential input signals; 2nd switch that is connected between 2nd power-supply terminal and 3rd transistor. Drive state of 1st and 2nd switches are controlled by a control signal.
    Type: Application
    Filed: June 2, 2010
    Publication date: February 3, 2011
    Applicant: NEC Electronics Corporation
    Inventors: Michimasa Yamaguchi, Kenichi Kawakami
  • Patent number: 7663407
    Abstract: A semiconductor device includes a pre-buffer for transferring a data signal on the basis of a first power supply voltage, a main buffer for amplifying and outputting the data signal transferred by the pre-buffer on the basis of a second power supply voltage different from the first power supply voltage, a switch unit for controlling a conductive state between the pre-buffer and the main buffer on the basis of a switch control signal, and a control circuit for generating the switch control signal for controlling the pre-buffer to set an output level of the pre-buffer to ground potential in accordance with transition of logical level of the switch control signal.
    Type: Grant
    Filed: June 24, 2008
    Date of Patent: February 16, 2010
    Assignee: NEC Electronics Corporation
    Inventors: Tomoya Nishitani, Kenichi Kawakami
  • Patent number: 7663707
    Abstract: A three-dimensional display device includes a liquid crystal display which has an image display surface which emits display light, a plurality of optical fibers, each of the optical fibers having a light-receiving end which receives the display light emitted from the image display surface and an emitting end which emits the display light, and a rotation device which rotates the optical fibers around a rotation axis perpendicular to the image display surface. The rotation radius of the light-receiving end and the rotation path of the emitting end of each of the optical fibers are set to have a one-to-one relationship.
    Type: Grant
    Filed: November 15, 2007
    Date of Patent: February 16, 2010
    Assignee: Technovates Co. Ltd.
    Inventors: Kenichi Kawakami, Tamae Kawakami
  • Publication number: 20090237108
    Abstract: Provided is a semiconductor integrated circuit including: an output circuit connected between a power supply (VDD0) and a ground (GND0), having an input connected to an input terminal, and having an output connected to an output terminal; and a power-supply-noise cancelling circuit connected between the input terminal and the output terminal to generate a current that cancels a current flowing from the power supply (VDD0) to the output terminal or a current flowing from the output terminal to the ground (GND0), based on a potential difference between the input terminal and the output terminal.
    Type: Application
    Filed: March 23, 2009
    Publication date: September 24, 2009
    Applicant: NEC Electronics Corporation
    Inventors: Masashi Kurokawa, Kenichi Kawakami
  • Patent number: 7492193
    Abstract: A driver circuit that prevents amplitude reduction at a high temperature comprises a differential pre-buffer circuit 22 for performing signal clamping by diodes 16 and 17 each having a nonlinear voltage-current characteristic with respect to an input signal and a differential output circuit 23 for amplifying output signals of the differential pre-buffer circuit 22, for output. The driver circuit further includes a temperature characteristic compensation circuit 44 for controlling direct currents to be passed through the diodes 16 and 17 based on a current to be passed through a diode 43 having a voltage-current characteristic with the same temperature coefficient as those of the diodes 16 and 17. A current related to constant currents I1 and I2 is supplied from the temperature characteristic compensation circuit 44 as a current that cancels the temperature characteristic of a fall in forward voltages of the diodes 16 and 17.
    Type: Grant
    Filed: January 5, 2006
    Date of Patent: February 17, 2009
    Assignee: NEC Electronics Corporation
    Inventor: Kenichi Kawakami
  • Publication number: 20090015292
    Abstract: A semiconductor device includes a pre-buffer for transferring a data signal on the basis of a first power supply voltage, a main buffer for amplifying and outputting the data signal transferred by the pre-buffer on the basis of a second power supply voltage different from the first power supply voltage, a switch unit for controlling a conductive state between the pre-buffer and the main buffer on the basis of a switch control signal, and a control circuit for generating the switch control signal for controlling the pre-buffer to set an output level of the pre-buffer to ground potential in accordance with transition of logical level of the switch control signal.
    Type: Application
    Filed: June 24, 2008
    Publication date: January 15, 2009
    Applicant: NEC Electronics Corporation
    Inventors: Tomoya Nishitani, Kenichi Kawakami
  • Publication number: 20080136981
    Abstract: A three-dimensional display device includes a liquid crystal display which has an image display surface which emits display light, a plurality of optical fibers, each of the optical fibers having a light-receiving end which receives the display light emitted from the image display surface and an emitting end which emits the display light, and a rotation device which rotates the optical fibers around a rotation axis perpendicular to the image display surface. The rotation radius of the light-receiving end and the rotation path of the emitting end of each of the optical fibers are set to have a one-to-one relationship.
    Type: Application
    Filed: November 15, 2007
    Publication date: June 12, 2008
    Applicant: TECHNOVATES CO., LTD.
    Inventors: Kenichi Kawakami, Tamae Kawakami
  • Publication number: 20070127614
    Abstract: Disclosed is a communication circuit including a clock selection circuit (20) which receives CDR multiple-phase clocks (16) from a PLL (1) to a CDR circuit (7), selects one of the CDR multiple-phase clock signals (16) responsive to a clock selection signal (21), and outputs the selected clock signal. At a time of the loopback test, the clock signal selected by the clock selection circuit (20) is used as a transmit clock (11). Transmit data is looped back from an input/output terminal (4) to a receiver circuit (6). Data from the receiver circuit (6) is supplied to the CDR circuit (7), and comparison between recovered data from the CDR circuit (7) and expected value data is made by a comparison circuit (8), thereby conducting the test. By changing a phase of the transmit clock (11) by the clock selection circuit (20), a delay time (=tTx+tRx) which is a sum of a transmit circuit delay time (tTx) and a receiver circuit delay time (tRx) can be varied.
    Type: Application
    Filed: December 6, 2006
    Publication date: June 7, 2007
    Applicant: NEC ELECTRONICS CORPORATION
    Inventor: Kenichi Kawakami
  • Publication number: 20060152253
    Abstract: A driver circuit that prevents amplitude reduction at a high temperature comprises a differential pre-buffer circuit 22 for performing signal clamping by diodes 16 and 17 each having a nonlinear voltage-current characteristic with respect to an input signal and a differential output circuit 23 for amplifying output signals of the differential pre-buffer circuit 22, for output. The driver circuit further includes a temperature characteristic compensation circuit 44 for controlling direct currents to be passed through the diodes 16 and 17 based on a current to be passed through a diode 43 having a voltage-current characteristic with the same temperature coefficient as those of the diodes 16 and 17. A current related to constant currents I1 and I2 is supplied from the temperature characteristic compensation circuit 44 as a current that cancels the temperature characteristic of a fall in forward voltages of the diodes 16 and 17.
    Type: Application
    Filed: January 5, 2006
    Publication date: July 13, 2006
    Applicant: NEC Electronics Corporation
    Inventor: Kenichi Kawakami
  • Patent number: 7058235
    Abstract: An imaging system of the present invention includes: a reflecting mirror having a geometry of one of two sheets of a two-sheeted hyperboloid; and an imaging section which includes an imaging device for receiving light concentrated by a lens having a center located in any position opposing the reflecting mirror on a rotation axis of the reflecting mirror, wherein the imaging system includes a correction section for performing coordinate transformation on captured image data obtained by capturing an image of a prescribed inspection drawing so as to produce a perspective transformed image data and for correcting distortion in the captured image based on a value regarding a distance between a lens position adapted for the coordinate transformation and a light-receiving surface of the imaging device.
    Type: Grant
    Filed: February 8, 2002
    Date of Patent: June 6, 2006
    Assignee: Sharp Kabushiki Kaisha
    Inventors: Setsunobu Wakamoto, Kiyoshi Kumata, Tohru Shigeta, Kenichi Kawakami, Kohichi Nakano
  • Patent number: 6947611
    Abstract: A perspective projection image creation system of the present invention includes: an optical system including a hyperboloidal mirror; an imaging section receiving light so as to create input image data; an image transformation section transforming input image data obtained by the imaging section into image data of a perspective projection; a scale model creation section transforming image data for an object in an object plane into image data for a scale model of the object such that a size of the scale model of the object corresponds to that of the object in a perspective projection image; an image combining section creating combined image data created by combining the perspective projection image data and the image data for the scale model; and a display section displaying the combined image data.
    Type: Grant
    Filed: May 9, 2002
    Date of Patent: September 20, 2005
    Assignee: Sharp Kabushiki Kaisha
    Inventors: Kenichi Kawakami, Kiyoshi Kumata
  • Patent number: 6831477
    Abstract: An identification is made of an abnormal condition in a motor due to an influence of a disturbance voltage, without addition of hardware, by estimating the disturbance voltage based on a target voltage and actual current flowing in the motor.
    Type: Grant
    Filed: March 5, 2003
    Date of Patent: December 14, 2004
    Assignee: Mitsubishi Denki Kabushiki Kaisha
    Inventors: Kouji Fukusumi, Masahiko Kurishige, Noriyuki Inoue, Seiji Sakanishi, Kenichi Kawakami, Takayuki Kifuku
  • Publication number: 20030179004
    Abstract: A judgment is made of an abnormal condition of a motor due to an influence of a disturbance voltage without addition of hardware by estimating the disturbance voltage on the basis of a target voltage and an actual current of the motor.
    Type: Application
    Filed: March 5, 2003
    Publication date: September 25, 2003
    Applicant: Mitsubishi Denki Kabushiki Kaisha
    Inventors: Kouji Fukusumi, Masahiko Kurishige, Noriyuki Inoue, Seiji Sakanishi, Kenichi Kawakami, Takayuki Kifuku