Abstract: A hybrid hydraulic excavator includes an engine, a generator motor, a capacitor, a cooling system being configured to cool the capacitor, and a controller. The cooling system includes a circulation mechanism being configured to circulate a cooling water, and a cooler being configured to cool the cooling water with output from the engine. The controller prohibits auto-stop of the engine when it is determined that the capacitor is overheated.

Abstract: An arithmetic circuit for quantizing pre-quantized data includes a first input register to store first-format pre-quantized data that includes a mantissa and an exponent, a second input register to store a quantization target exponent, an exponent-correction-value indicating unit to indicate an exponent correction value, an exponent generating unit to generate a quantized exponent obtained by subtracting the exponent correction value from the quantization target exponent, a shift amount generating unit to generate a shift amount obtained by subtracting the exponent of the pre-quantized data and the exponent correction value from the quantization target exponent, a shift unit to generate a quantized mantissa obtained by shifting the mantissa of the pre-quantized data by the shift amount generated by the shift amount generating unit, and an output register to store quantized data that includes the quantized exponent generated by the exponent generating unit and the quantized mantissa generated by the shift unit

Abstract: An arithmetic operation circuit includes: an extractor circuit that extracts one or a plurality of bits consecutive from a most significant bit or from a least significant bit of a binary number; a sum register that stores an X-adic sum, where X is an integer more than two; and an update circuit that updates the stored X-adic sum with a value obtained by adding a first X-adic number to be cyclically multiplied by a certain coefficient to the X-adic sum in accordance with the extracted one or plurality of bits.

Abstract: An arithmetic circuit calculates a correction value for a value that is obtained by an add-subtract operation of two values and that is expressed in a predetermined fixed precision.

Abstract: An arithmetic circuit for performing division based on restoring division includes an intermediate remainder register configured to store an intermediate remainder, a quotient prediction circuit configured to perform, based on information about two most significant digits of the intermediate remainder and a most significant digit of a divisor, quotient prediction having lower precision than a highest precision obtainable from the information, thereby generating a prediction result, a fixed-value multiplication circuit configured to output one or more N-th (N: integer) multiples of the divisor selected in response to the prediction result, one or more subtracters configured to subtract, from the intermediate remainder, the one or more N-th multiples of the divisor output from the fixed-value multiplication circuit, and a partial quotient calculating circuit configured to obtain a partial quotient in response to one or more carry-out bits of one or more subtractions performed by the one or more subtracters.

Abstract: A multiplying device includes: a circuit which left-shifts a mantissa part of a floating-point number being a multiplicand by a shift amount; a circuit which calculates a digit number of the mantissa part of the multiplier by subtracting the count value from the digit number of the fixed precision of the mantissa part; a multiplying circuit which outputs an intermediate product on a digit-by-digit basis of the mantissa part of the multiplier based on the mantissa part of the left-shifted multiplicand and the mantissa part of the multiplier; an adding circuit which adds exponent parts of the multiplicand and the multiplier; and a control circuit which outputs the intermediate product output by the multiplying circuit, as a mantissa part of a floating-point number being a product and outputs the value output by the adding circuit, as an exponent part of the floating-point number being the product.

Abstract: A dividing device includes: shifting circuits which left-shift the mantissa parts of the dividend and the divisor by a first and a second count values; a digit number arithmetic circuit which calculates a quotient digit number expected value based on the first count value and the second count value; a dividing circuit which outputs a quotient and a remainder in sequence on a digit-by-digit basis based on the mantissa parts of the dividend and the divisor left-shifted by the shifting circuits; a subtracting circuit which subtracts an exponent part of the floating-point number being the divisor from an exponent part of the floating-point number being the dividend to output a resultant value; and a control circuit which outputs a mantissa part and an exponent part of a floating-point number being a quotient.

Abstract: An arithmetic circuit for calculating a correction value for a result of an arithmetic operation that is an addition or subtraction performed with respect to a first floating-point number and a second floating-point number smaller than the first floating-point number. The arithmetic circuit includes a generation unit configured to generate a significand of a normalized correction value for the result of the arithmetic operation and an exponent of the normalized correction value based on the sign, the significand, and the exponent of the second floating-point number when a difference between a result of subtracting the leading zero count of the significand of the first floating-point number from the corresponding exponent and a result of subtracting a leading zero count of the significand of the second floating-point number from the corresponding exponent is larger than or equal to a second predetermined value.

Abstract: An arithmetic circuit includes a circuit to output n-th multiples of a multiplicand, a circuit to output an XOR operation result that is a result of performing an exclusive logical sum operation between the multiplicand and a result of shifting the multiplicand to left by one bit, a circuit to output a first selection signal in response to a first portion of a multiplier, a circuit to output a second selection signal in response to a second portion of the multiplier, a circuit to select, in response to the first selection signal, one of the n-th multiples of the multiplicand and the XOR operation result, a circuit to select, in response to the second selection signal, one of the n-th multiples of the multiplicand and the XOR operation result, and a circuit to output a result of adding up the first partial product and the second partial product.

Abstract: An arithmetic circuit includes a storage circuit configured to store a decimal floating point number in an encoded state, a detection circuit configured to detect a pattern of an arrangement of zeros from a bit pattern of the decimal floating point number by decoding the decimal floating point number stored in the storage circuit, and a leading-zero-count circuit configured to generate data indicative of a number of consecutive zeros starting from a most significant bit or from a least significant bit in a significand of the decimal floating point number in response to a detection result obtained by the detection circuit.

Abstract: At a front-end side opposite to a head-fixing-member-attachment side, a protection member has an inclined plane sloped up from a head side toward the opposite outer side in a direction in which liquid ejecting heads are arranged in a row. The surface of the front end is located at a position that is not closer to a head-fixing member in comparison with the nozzle surface of each of the liquid ejecting heads attached to the head-fixing member or level therewith. A recess is formed at a part of the inclined plane. In a state in which one of the caps faces the protection member and, in addition, each of the remaining caps is in contact with the nozzle surface of the liquid ejecting head, a part of the cap facing the protection member is in the recess, which ensures that the cap is not in contact with the protection member.

Abstract: A predictor configured to predict a parity value of a Carry-Less multiplication result of a multiplicand data string and a multiplier data string being two data strings in which q (q is a natural number) data units being p-bit (p is a natural number equal to two or above) data, includes a unit configured to predict a parity value of a first data unit from lower order in a result data string representing the multiplication result based on a value and a parity value of a first data unit from lower order in each of the two data strings; and a unit configured to predict a parity value for data at a high-order p?1 bit of the result data string based on a value and a parity value for a q-th data unit from lower order in each of the two data strings.

Abstract: A liquid ejecting apparatus comprising: a liquid reservoir unit, a liquid ejection head, a supply channel, a collecting channel; and a first pressure applied to the downstream side of the valve member in the circulation channel by the suction pump is larger than a second pressure on the downstream side of the valve member in the circulation channel required for causing the film to act so that the valve member opens the circulation channel, and a sum of a waterhead pressure determined by the height from the liquid reservoir unit to the circulation channel opened and closed by the valve member provided in each of the circulation channel and the first pressure is smaller than the second pressure.

Abstract: In a drive circuit for display, the drive circuit includes: a pixel signal generation section generating a pixel signal and supplying the pixel signal to a display section, the pixel signal being inverted every frame period in each of a first period and a second period, the first period and the second period being alternately provided; and a writing control section controlling writing of the pixel signal into the display section to be performed in each of the first period and the second period except for a leading period, the leading period being provided in each of the first period and the second period, and having a predetermined length from start of each of the first period and the second period.

Abstract: An arithmetic circuit calculates a correction value for a value that is obtained by an add-subtract operation of two values and that is expressed in a predetermined fixed precision.

Abstract: An arithmetic circuit for quantizing pre-quantized data includes a first input register to store first-format pre-quantized data that includes a mantissa and an exponent, a second input register to store a quantization target exponent, an exponent-correction-value indicating unit to indicate an exponent correction value, an exponent generating unit to generate a quantized exponent obtained by subtracting the exponent correction value from the quantization target exponent, a shift amount generating unit to generate a shift amount obtained by subtracting the exponent of the pre-quantized data and the exponent correction value from the quantization target exponent, a shift unit to generate a quantized mantissa obtained by shifting the mantissa of the pre-quantized data by the shift amount generated by the shift amount generating unit, and an output register to store quantized data that includes the quantized exponent generated by the exponent generating unit and the quantized mantissa generated by the shift unit

Abstract: An arithmetic circuit for rounding pre-rounded data includes a first register to store first-format pre-rounded data that includes a mantissa of a fixed-precision floating-point number using a base-N numbering system, and includes an exponent for the mantissa, a second register to store rounding precision data indicative of precision for rounding the pre-rounded data, a leading zero counting unit to count consecutive zeros starting from a most significant bit of the mantissa stored in the first register, an exponent generating unit to generate a post-round exponent indicative of an exponent for a rounded significant by subtracting the number of zeros counted by the leading zero counting unit and the rounding precision data from a sum of one and the exponent stored in the first register, and an output register to store the post-round exponent and a rounding-add value that is to be added to a digit at which rounding is performed.

Abstract: An arithmetic operation circuit includes: an extractor circuit that extracts one or a plurality of bits consecutive from a most significant bit or from a least significant bit of a binary number; a sum register that stores an X-adic sum, where X is an integer more than two; and an update circuit that updates the stored X-adic sum with a value obtained by adding a first X-adic number to be cyclically multiplied by a certain coefficient to the X-adic sum in accordance with the extracted one or plurality of bits.

Abstract: A liquid ejecting apparatus includes: a plurality of liquid ejecting heads for ejecting liquid from nozzles, the liquid ejecting heads arranged side by side with a gap each therebetween, each of the liquid ejecting heads including one side surface in a direction of side-by-side arrangement; the other side surface in the direction of side-by-side arrangement; a groove; and intersecting side surfaces, which intersect with the side surfaces, wherein the groove is formed in either one, or both, of opposed side surfaces of each two adjacent liquid ejecting heads arranged side by side, and the groove formed in the side surface or formed in each of the side surfaces extends from one of the intersecting side surfaces to the other.

Abstract: There is provided a technique capable of executing a predetermined processing while continuing a database processing. Firstly, the database to be operated is switched from the main database to a duplicate database. The predetermined processing is executed to the main database which becomes the non-operation mode by the switching. Next, a database access request is distributed to the duplicate database which becomes the operation mode by the switching, thereby performing the database processing. Update information indicating the content of the update processing performed to the duplicate database is output. The output update information is reflected on the main data base for which the predetermined processing has been executed. After this, the database to be operated is switched from the duplicate database to the main database.