Abstract: A cell signal measurement electrode plate includes a first transistor including a gate terminal connected to a first selection line and a source terminal connected to a second selection line, a second transistor including a gate terminal connected to a drain terminal of the first transistor, a source terminal connected to an electrode, and a drain terminal connected to a common wiring line, and a first capacitor including one capacitance electrode connected to the drain terminal of the first transistor and another capacitance electrode connected to a capacitance element potential fixing wiring line.

Abstract: A scanning antenna includes a transmission and/or reception region including a plurality of antenna units and a non-transmission and/or reception region other than the transmission and/or reception region. The scanning antenna includes a TFT substrate, a slot substrate, a liquid crystal layer provided between the TFT substrate and the slot substrate, a seal portion provided in the non-transmission and/or reception region and surrounding the liquid crystal layer, and a reflective conductive plate disposed opposing a second main surface of a second dielectric substrate with a dielectric layer interposed between the reflective conductive plate and the second main surface. The slot electrode includes an opening or a recessed portion formed in the non-transmission and/or reception region and in the region surrounded by the seal portion.

Abstract: A liquid crystal device includes a first substrate (TFT substrate) including a first dielectric substrate, a second substrate (slot substrate) including a second dielectric substrate, a liquid crystal layer provided between the first substrate and the second substrate and in all of an effective region and a portion of a non-effective region, a sealing seal portion configured to define the maximum value of the area of the liquid crystal layer when viewed from a normal direction of the first or second dielectric substrate, a cell gap control seal portion configured to define the minimum value of the thickness of the liquid crystal layer in the effective region, and a buffer portion provided in contact with the liquid crystal layer in the non-effective region and that deforms more easily due to external force than the first and second dielectric substrates in the effective region. The buffer portion includes a sheet and a joining section that joins the sheet and the first or second dielectric substrate.

Abstract: Provided is a microfluidic device that, as compared with a conventional microfluidic device, (i) is smoother in surface of a water-repellent layer provided above a segment electrode and (ii) makes it easier for microfluid provided in the surface of the water-repellent layer to slide. A microfluidic device (1) includes: an array substrate (10) including a plurality of electrodes (14); and a counter substrate (40) including at least one electrode (42), the array substrate (10) and the counter substrate (40) having therebetween an internal space (50) in which to cause an electroconductive droplet (51) to move across the plurality of electrodes (14), and the plurality of electrodes (14) being provided on a first flattening resin layer (13) and each being a light-blocking metal electrode.

Abstract: A scanning antenna includes a transmission and/or reception region including a plurality of antenna units and a non-transmission and/or reception region other than the transmission and/or reception region. The scanning antenna includes a TFT substrate, a slot substrate, a liquid crystal layer provided between the TFT substrate and the slot substrate, a seal portion provided in the non-transmission and/or reception region and surrounding the liquid crystal layer, and a reflective conductive plate disposed opposing a second main surface of a second dielectric substrate with a dielectric layer interposed between the reflective conductive plate and the second main surface. The slot electrode includes an opening or a recessed portion formed in the non-transmission and/or reception region and in the region surrounded by the seal portion.

Abstract: A scanning antenna includes a TFT substrate including a plurality of TFTs supported by a first dielectric substrate and a plurality of patch electrodes, a slot substrate including a slot electrode supported by a second dielectric substrate, a liquid crystal layer provided between the TFT substrate and the slot substrate, and a reflective conductive plate disposed opposing the second dielectric substrate across a dielectric layer. The slot electrode includes a plurality of slots disposed corresponding to the plurality of patch electrodes, each patch electrode is connected to a drain of the corresponding TFT, the slot electrode includes Cu layers, and lower metal layers and/or an upper metal layer, and the lower metal layer and/or the upper metal layer decrease about a half or more of a tensile stress of the Cu layer.

Abstract: A TFT substrate includes a dielectric substrate and a plurality of antenna unit regions arranged on the dielectric substrate. Each of the plurality of antenna unit regions has a TFT and a patch electrode electrically connected to the drain electrode of the TFT. The patch electrode includes a first electrode layer formed of the same conductive film as the gate electrode of the TFT and a second electrode layer formed of the same conductive film as the source electrode of the TFT.

Abstract: A scanning antenna includes a TFT substrate including a plurality of TFTs supported by a first dielectric substrate and a plurality of patch electrodes, a slot substrate including a slot electrode supported by a second dielectric substrate, a liquid crystal layer provided between the TFT substrate and the slot substrate, and a reflective conductive plate disposed opposing the second dielectric substrate across a dielectric layer. The slot electrode includes a plurality of slots disposed corresponding to the plurality of patch electrodes, each patch electrode is connected to a drain of the corresponding TFT, the slot electrode includes Cu layers, and lower metal layers and/or an upper metal layer, and the lower metal layer and/or the upper metal layer decrease about a half or more of a tensile stress of the Cu layer.

Abstract: A liquid crystal device includes a first substrate (TFT substrate) including a first dielectric substrate, a second substrate (slot substrate) including a second dielectric substrate, a liquid crystal layer provided between the first substrate and the second substrate and in all of an effective region and a portion of a non-effective region, a sealing seal portion configured to define the maximum value of the area of the liquid crystal layer when viewed from a normal direction of the first or second dielectric substrate, a cell gap control seal portion configured to define the minimum value of the thickness of the liquid crystal layer in the effective region, and a buffer portion provided in contact with the liquid crystal layer in the non-effective region and that deforms more easily due to external force than the first and second dielectric substrates in the effective region. The buffer portion includes a sheet and a joining section that joins the sheet and the first or second dielectric substrate.

Abstract: A TFT substrate includes a dielectric substrate and a plurality of antenna unit regions arranged on the dielectric substrate. Each of the plurality of antenna unit regions has a TFT and a patch electrode electrically connected to the drain electrode of the TFT. The patch electrode includes a first electrode layer formed of the same conductive film as the gate electrode of the TFT and a second electrode layer formed of the same conductive film as the source electrode of the TFT.

Abstract: An active matrix substrate includes an insulating substrate (100); a surface coating film (110) that covers at least a part of a surface of the insulating substrate; an insulating light-transmitting film (204) provided on the insulating substrate including the surface coating film; gate lines; a gate insulating film; thin film transistors; data lines; and lead-out lines (115). In a peripheral portion of the insulating substrate, an area where the insulating light-transmitting film is not provided is formed. The lead-out line is provided so as to intersect with an outer circumference end of the insulating light-transmitting film, when viewed in a direction vertical to the insulating substrate. In the area where the insulating light-transmitting film is not provided, the surface coating film is also provided on a part in contact with the outer circumference end of the insulating light-transmitting film.

Abstract: Provided is a microfluidic device that, as compared with a conventional microfluidic device, (i) is smoother in surface of a water-repellent layer provided above a segment electrode and (ii) makes it easier for microfluid provided in the surface of the water-repellent layer to slide. A microfluidic device (1) includes: an array substrate (10) including a plurality of electrodes (14); and a counter substrate (40) including at least one electrode (42), the array substrate (10) and the counter substrate (40) having therebetween an internal space (50) in which to cause an electroconductive droplet (51) to move across the plurality of electrodes (14), and the plurality of electrodes (14) being provided on a first flattening resin layer (13) and each being a light-blocking metal electrode.

Abstract: A semiconductor device is provided with an oxide semiconductor thin-film transistor (TFT); a calibration electrode that is positioned so as to face an oxide semiconductor layer with an insulating layer therebetween, and, when viewed from the direction of the substrate normal line, overlaps at least part of a gate electrode with the oxide semiconductor layer interposed therebetween; and a calibration voltage setting circuit that determines the voltage to be applied to the calibration electrode. The calibration voltage setting circuit is provided with: a monitor TFT that is configured using a second oxide semiconductor layer, which is substantially the same as the oxide semiconductor layer of the oxide semiconductor TFT; a detection circuit that is configured so as to be able to measure the device characteristics of the monitor TFT; and a voltage determination circuit that determines the voltage to be applied to the calibration electrode on the basis of the measured device characteristics.

Abstract: An array board (a semiconductor device) 11b includes a display area TFT (a display area transistor) 17, a non-display area TFT (a non-display area transistor) 29, an upper insulator 31, and a lower insulator 30. The display area TFT 17 is arranged in a display area AA. The non-display area TFT 29 is arranged in a non-display area NAA. The upper insulator 31 is arranged in the non-display area NAA and formed from a second interlayer insulation film 41. The lower insulator 30 is arranged in the non-display area and formed from a first interlayer insulation film 39. The lower insulator 30 is arranged below the upper insulator 31 such that they are layered.

Abstract: This semiconductor device (101) includes: a substrate (1); a thin-film transistor (10) which includes an oxide semiconductor layer (6) as its active layer; a protective layer (11) covering the thin-film transistor; a metal layer (9d, 9t) interposed between the protective layer (11) and the substrate (1); a transparent conductive layer (13, 13t) formed on the protective layer (11); and a connecting portion (20, 30) to electrically connect the metal layer (9d, 9t) and the transparent conductive layer (13, 13t) together. The connecting portion (20, 30) includes an oxide connecting layer (6a, 6t) which is formed out of a same oxide film as a oxide semiconductor layer (6) and which has a lower electrical resistance than the oxide semiconductor layer (6). The metal layer (9d, 9t) is electrically connected to the transparent conductive layer (13, 13t) via the oxide connecting layer (6a, 6t).

Abstract: An array board (a semiconductor device) 11b includes a display area TFT (a display area transistor) 17, a non-display area TFT (a non-display area transistor) 29, an upper insulator 31, and a lower insulator 30. The display area TFT 17 is arranged in a display area AA. The non-display area TFT 29 is arranged in a non-display area NAA. The upper insulator 31 is arranged in the non-display area NAA and formed from a second interlayer insulation film 41. The lower insulator 30 is arranged in the non-display area and formed from a first interlayer insulation film 39. The lower insulator 30 is arranged below the upper insulator 31 such that they are layered.

Abstract: A semiconductor device is provided with an oxide semiconductor thin-film transistor (TFT); a calibration electrode that is positioned so as to face an oxide semiconductor layer with an insulating layer therebetween, and, when viewed from the direction of the substrate normal line, overlaps at least part of a gate electrode with the oxide semiconductor layer interposed therebetween; and a calibration voltage setting circuit that determines the voltage to be applied to the calibration electrode. The calibration voltage setting circuit is provided with: a monitor TFT that is configured using a second oxide semiconductor layer, which is substantially the same as the oxide semiconductor layer of the oxide semiconductor TFT; a detection circuit that is configured so as to be able to measure the device characteristics of the monitor TFT; and a voltage determination circuit that determines the voltage to be applied to the calibration electrode on the basis of the measured device characteristics.

Abstract: The present invention provides an active matrix substrate including a thin film transistor that sufficiently achieves high reliability and a low capacitance, a production method for the active matrix substrate without an increase in the number of photomasks, a display device including the active matrix substrate, and a production method for the display device. The active matrix substrate of the present invention includes a thin film transistor that includes a semiconductor layer consisting of an oxide semiconductor. The active matrix substrate includes at least the semiconductor layer consisting of the oxide semiconductor, an etching stopper layer, and an interlayer insulating film formed from a spin-on-glass material. In the plan view of the principal surface of the substrate, the etching stopper layer covers at least part of the semiconductor layer, and the interlayer insulating film covers at least part of the etching stopper layer.

Abstract: This semiconductor device (101) includes: a substrate (1); a thin-film transistor (10) which includes an oxide semiconductor layer (6) as its active layer; a protective layer (11) covering the thin-film transistor; a metal layer (9d, 9t) interposed between the protective layer (11) and the substrate (1); a transparent conductive layer (13, 13t) formed on the protective layer (11); and a connecting portion (20, 30) to electrically connect the metal layer (9d, 9t) and the transparent conductive layer (13, 13t) together. The connecting portion (20, 30) includes an oxide connecting layer (6a, 6t) which is formed out of a same oxide film as a oxide semiconductor layer (6) and which has a lower electrical resistance than the oxide semiconductor layer (6). The metal layer (9d, 9t) is electrically connected to the transparent conductive layer (13, 13t) via the oxide connecting layer (6a, 6t).

Abstract: A drain electrode (17) includes (i) a lower drain electrode (17a) stacked on a semiconductor layer (14) so as to partially cover an upper surface of the semiconductor layer (14) and (ii) an upper drain electrode (17b). The semiconductor layer (14), the lower drain electrode (17a), and the upper drain electrode (17b) form steps. In a step part where the steps are formed, a distance between a periphery of the lower drain electrode (17a) and a periphery of the upper drain electrode (17b) is more than 0.4 ?m but less than 1.5 ?m.