Patents by Inventor Kenichi Maeda

Kenichi Maeda has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20210301258
    Abstract: The present disclosure relates to a method for producing dental pulp-derived cells enriched with pluripotent stem cells including: (a) digesting dental pulp with a protease to prepare a dental pulp suspension; (b) culturing the suspension to proliferate pluripotent stem cells contained in the suspension; (c) freezing the proliferated pluripotent stem cells in a state in which the pluripotent stem cells are suspended in a first cryopreservation liquid; (d) thawing the frozen pluripotent stem cells; (e) culturing the thawed pluripotent stem cells in a state in which the pluripotent stem cells are adhered to surfaces of particles to proliferate the pluripotent stem cells on the surfaces of the particles; and (f) bringing the particles into contact with a protease to separate the pluripotent stem cells adhered to the surfaces of the particles from the particles.
    Type: Application
    Filed: July 30, 2019
    Publication date: September 30, 2021
    Applicants: JCR Pharmaceuticals Co., Ltd., Teijin Limited
    Inventors: Kiwamu Imagawa, Kotaro Minami, Kenichi Maeda, Yuki Hosoda, Shunsuke Watanabe, Kazutoshi Sato, Yasuna Higashiguchi, Takashi Kushida, Ayumi Ishiwari
  • Publication number: 20210291927
    Abstract: A saddle riding type vehicle having a front fork that supports a front wheel, a head pipe that rotationally movably supports the front fork, a down frame extending downward from the head pipe, a front wheel brake supported by the front fork, to brake the front wheel, a braking force adjustment device that controls braking force of the front wheel brake, and output piping that connects the braking force adjustment device and the front wheel brake, the output piping has metal piping extending forward from the braking force adjustment device disposed behind the down frame, flexible piping, and a connecting member that connects the metal piping and the flexible piping. The connecting member is disposed in front of the down frame, and the flexible piping extends forward from the connecting member, to be connected to the front wheel brake.
    Type: Application
    Filed: May 17, 2019
    Publication date: September 23, 2021
    Inventors: Shinichi Yamada, Kenichi Maeda
  • Publication number: 20210291928
    Abstract: A saddle riding type vehicle n hick a braking force adjustment device, a master cylinder and a reserve tank can be compactly arranged. In, the saddle riding type vehicle having a braking force adjustment device that controls braking force of a vehicle wheel, a master cylinder for a rear wheel that outputs brake hydraulic pressure in response to operation of a brake pedal, and a reserve tank that stores brake fluid for the master cylinder for the rear wheel, in a vehicle side view, the reserve tank is disposed above the master cylinder for the rear wheel, and the braking force adjustment device is provided between the master cylinder for the rear wheel and the reserve tank.
    Type: Application
    Filed: May 17, 2019
    Publication date: September 23, 2021
    Inventors: Shinichi Yamada, Kenichi Maeda
  • Patent number: 11110874
    Abstract: A method for joining members according to an embodiment of the present invention includes: providing a bumper stay including two integrated pipe portions extending in an identical direction, the bumper stay including a recess provided between the pipe portions being adjacent to each other, the recess extending in a longitudinal direction of the pipe portions from end surfaces of the pipe portions, a part of the recess serving as a locking portion, and a bumper beam including a rear inclined wall formed with two hole portions into which the pipe portions of the bumper stay are insertable respectively; inserting the bumper stay into the hole portions of the bumper beam until the locking portion abuts on the rear inclined wall; and pipe-expanding an insertion portion of the bumper stay into the bumper beam to join the insertion portion to the bumper beam by press-fitting.
    Type: Grant
    Filed: March 13, 2018
    Date of Patent: September 7, 2021
    Assignee: Kobe Steel, Ltd.
    Inventors: Yasuhiro Maeda, Toru Hashimura, Kenichi Watanabe, Ryohei Yukishige, Taiki Yamakawa
  • Publication number: 20210200434
    Abstract: A device includes a host including a main memory, and semiconductor memory including a nonvolatile semiconductor memory, memory unit, and controller. The nonvolatile semiconductor memory stores first address information. The memory unit stores second address information as part of the first address information. The controller accesses the nonvolatile semiconductor memory based on the second address information. Third address information is stored in the main memory, and is part or all of the first address information. The controller uses the third address information when accessing the nonvolatile semiconductor memory if address information to be referred is not stored in the second address information.
    Type: Application
    Filed: March 12, 2021
    Publication date: July 1, 2021
    Applicant: TOSHIBA MEMORY CORPORATION
    Inventors: Atsushi KUNIMATSU, Kenichi MAEDA
  • Publication number: 20210155172
    Abstract: A vehicle includes a radiator including a fan, a driving seat provided on a rear side of the radiator, a dashboard disposed on the rear side of the radiator and on a front side of the driving seat, and a heat shield plate disposed between the radiator and the dashboard. According to this structure, it is possible to prevent a device (for example, an electric component disposed on the dashboard) disposed on the rear side of the radiator from directly contacting air that receives heat of the radiator.
    Type: Application
    Filed: November 24, 2020
    Publication date: May 27, 2021
    Inventors: Kenichi MAEDA, Shinichiro NAKAMURA
  • Publication number: 20210141746
    Abstract: According to one embodiment, a memory device includes a nonvolatile memory, a volatile memory, a controller, and a board. The nonvolatile memory stores data. The volatile memory holds a part of the data stored in the nonvolatile memory. The memory controller controls the volatile memory and the nonvolatile memory. The nonvolatile memory, the volatile memory, and the memory controller are provided on the board. The memory controller transmits an interrupt signal to a request source, when the volatile memory does not have any data corresponding to an address which the request source requests to access.
    Type: Application
    Filed: January 22, 2021
    Publication date: May 13, 2021
    Inventors: Toshio Fujisawa, Nobuhiro Kondo, Shoji Sawamura, Kenichi Maeda, Atsushi Kunimatsu
  • Patent number: 10949092
    Abstract: A device includes a host including a main memory, and semiconductor memory including a nonvolatile semiconductor memory, memory unit, and controller. The nonvolatile semiconductor memory stores first address information. The memory unit stores second address information as part of the first address information. The controller accesses the nonvolatile semiconductor memory based on the second address information. Third address information is stored in the main memory, and is part or all of the first address information. The controller uses the third address information when accessing the nonvolatile semiconductor memory if address information to be referred is not stored in the second address information.
    Type: Grant
    Filed: June 13, 2019
    Date of Patent: March 16, 2021
    Assignee: TOSHIBA MEMORY CORPORATION
    Inventors: Atsushi Kunimatsu, Kenichi Maeda
  • Patent number: 10929315
    Abstract: According to one embodiment, a memory device includes a nonvolatile memory, a volatile memory, a controller, and a board. The nonvolatile memory stores data. The volatile memory holds a part of the data stored in the nonvolatile memory. The memory controller controls the volatile memory and the nonvolatile memory. The nonvolatile memory, the volatile memory, and the memory controller are provided on the board. The memory controller transmits an interrupt signal to a request source, when the volatile memory does not have any data corresponding to an address which the request source requests to access.
    Type: Grant
    Filed: June 29, 2018
    Date of Patent: February 23, 2021
    Assignee: Toshiba Memory Corporation
    Inventors: Toshio Fujisawa, Nobuhiro Kondo, Shoji Sawamura, Kenichi Maeda, Atsushi Kunimatsu
  • Patent number: 10776007
    Abstract: A memory management device of an example of the invention controls writing into and reading from a main memory including a nonvolatile semiconductor memory and a volatile semiconductor memory in response to a writing request and a reading request from a processor. The memory management device includes a coloring information storage unit that stores coloring information generated based on a data characteristic of write target data to be written into at least one of the nonvolatile semiconductor memory and the volatile semiconductor memory, and a writing management unit that references the coloring information to determines a region into which the write target data is written from the nonvolatile semiconductor memory and the volatile semiconductor memory.
    Type: Grant
    Filed: November 11, 2015
    Date of Patent: September 15, 2020
    Assignee: TOSHIBA MEMORY CORPORATION
    Inventors: Atsushi Kunimatsu, Masaki Miyagawa, Hiroshi Nozue, Kazuhiro Kawagome, Hiroto Nakai, Hiroyuki Sakamoto, Tsutomu Owa, Tsutomu Unesaki, Reina Nishino, Kenichi Maeda, Mari Takada
  • Publication number: 20190390333
    Abstract: There is provided a technique that includes executing a process recipe for processing a substrate; and executing a correction recipe for checking a characteristic value of a supply valve installed at a process gas supply line, wherein the act of executing the correction recipe comprises: supplying an inert gas into the process gas supply line for a certain period of time in a state where an adjusting valve that is installed at an exhaust portion of a process furnace and adjusts an internal pressure of the process furnace is fully opened; detecting a pressure value in a supply pipe provided with the supply valve while supplying the inert gas into the process gas supply line in the state where the adjusting valve is fully opened; and calculating the characteristic value of the supply valve based on the detected pressure value.
    Type: Application
    Filed: June 25, 2019
    Publication date: December 26, 2019
    Applicant: KOKUSAI ELECTRIC CORPORATION
    Inventors: Masaya NISHIDA, Nobuhito SHIMA, Akihiro SATO, Yosuke KUWATA, Kenichi MAEDA
  • Patent number: 10467020
    Abstract: According to one embodiment, the memory device includes a non-volatile memory, a volatile memory, and a controller. The controller carries out the transition to two different sleep states depending on a sleep instruction from the host device and saves sleep state information indicating the sleep state after the transition to the host-side storage device. Upon receiving a return instruction from the host device, the controller carries out return processing in accordance with the sleep state information stored in the host-side storage device.
    Type: Grant
    Filed: September 2, 2016
    Date of Patent: November 5, 2019
    Assignee: TOSHIBA MEMORY CORPORATION
    Inventors: Yuji Izumi, Kenichi Maeda, Kenji Funaoka, Reina Nishino, Toshio Fujisawa, Nobuhiro Kondo
  • Publication number: 20190294331
    Abstract: A device includes a host including a main memory, and semiconductor memory including a nonvolatile semiconductor memory, memory unit, and controller. The nonvolatile semiconductor memory stores first address information. The memory unit stores second address information as part of the first address information. The controller accesses the nonvolatile semiconductor memory based on the second address information. Third address information is stored in the main memory, and is part or all of the first address information. The controller uses the third address information when accessing the nonvolatile semiconductor memory if address information to be referred is not stored in the second address information.
    Type: Application
    Filed: June 13, 2019
    Publication date: September 26, 2019
    Applicant: TOSHIBA MEMORY CORPORATION
    Inventors: Atsushi KUNIMATSU, Kenichi MAEDA
  • Patent number: 10402864
    Abstract: According to one embodiment, a storage unit, a management unit that acquires attributes of communication apparatuses from a plurality of the communication apparatuses and stores identifiers of the communication apparatuses and the attributes in the storage unit in association with each other as communication apparatus information, and a selection unit that selects a distributor apparatus that is the communication apparatus distributing a content to the other communication apparatuses as a radio signal based on the communication apparatus information are included.
    Type: Grant
    Filed: December 23, 2014
    Date of Patent: September 3, 2019
    Assignee: TOSHIBA MEMORY CORPORATION
    Inventors: Arata Miyamoto, Kenichi Maeda, Masahiro Ishiyama, Shinya Murai, Hiroto Nakai
  • Patent number: 10335439
    Abstract: [Problem] To provide a method for producing human corneal epithelial sheet, wherein the human corneal epithelial-derived cells obtained by culturing human corneal epithelial cells are cultured on an amnion substrate. [Solution] A method for culturing human corneal epithelial cells using mesenchymal stem cells as the feeder cells; and a method for culturing human corneal epithelial cells using a medium containing a ROCK inhibitor, a phosphodiesterase inhibitor, a MAP kinase inhibitor and a TGF-? receptor inhibitor in various combinations.
    Type: Grant
    Filed: March 9, 2014
    Date of Patent: July 2, 2019
    Assignees: JCR Pharmaceuticals Co., Ltd., Kyoto Prefectural Public University Corporation
    Inventors: Kiwamu Imagawa, Kenichi Maeda, Yuki Hosoda, Shuichi Yokoyama, Naoki Okumura, Noriko Koizumi, Shigeru Kinoshita
  • Patent number: 10331356
    Abstract: A device includes a host including a main memory, and semiconductor memory including a nonvolatile semiconductor memory, memory unit, and controller. The nonvolatile semiconductor memory stores first address information. The memory unit stores second address information as part of the first address information. The controller accesses the nonvolatile semiconductor memory based on the second address information. Third address information is stored in the main memory, and is part or all of the first address information. The controller uses the third address information when accessing the nonvolatile semiconductor memory if address information to be referred is not stored in the second address information.
    Type: Grant
    Filed: December 6, 2017
    Date of Patent: June 25, 2019
    Assignee: TOSHIBA MEMORY CORPORATION
    Inventors: Atsushi Kunimatsu, Kenichi Maeda
  • Patent number: 10278233
    Abstract: According to one embodiment, a communication apparatus includes a radio interface unit that sends a data message to a receiver and extracts, when a message sent by the receiver via unicast with an optimized transmission rate is received, rate information indicating the optimized transmission rate of the receiver from the received message, a message processor that generates the data message, in which a multicast identifier indicating a multicast group is a destination, and outputs the data message to the radio interface unit, and a selector that selects, according to the rate information, a data message transmission rate to send the data message.
    Type: Grant
    Filed: March 4, 2016
    Date of Patent: April 30, 2019
    Assignee: TOSHIBA MEMORY CORPORATION
    Inventors: Yujen Lai, Yosuke Bando, Kenichi Maeda, Masahiro Ishiyama, Ren Sakata, Hiroki Kudo, Takeshi Sakoda
  • Patent number: 10187818
    Abstract: According to one embodiment, a communication apparatus includes a congestion degree calculating unit and an operation mode setting unit. The congestion degree calculating unit calculates a third congestion degree related to wireless communication based on a first congestion degree of first wireless communication and a second congestion degree of second wireless communication. In the first wireless communication, peer-to-peer communication is performed directly between communication apparatuses, and in the second wireless communication, communication is performed through a wireless communication device. The operation mode setting unit switches an operation mode of the first wireless communication based on the third congestion degree to either of a mode in which the communication apparatus transmits content or a mode in which the communication apparatus receives content.
    Type: Grant
    Filed: March 1, 2016
    Date of Patent: January 22, 2019
    Assignee: TOSHIBA MEMORY CORPORATION
    Inventors: Yosuke Bando, Yujen Lai, Youyang Ng, Kenichi Maeda, Takeshi Sakoda, Takaomi Murakami, Yusuke Doi, Masahiro Ishiyama
  • Patent number: 10146483
    Abstract: According to one embodiment, a memory system is connectable to a host including a first memory. The memory system includes a non-volatile second memory, a volatile third memory, and a controller. The controller uses the third memory as a work memory, and executes data transfer between the host and the second memory. The controller receives a first command to change a power mode from the host. The controller transfers first data to the first memory and transfers second data to the second memory in response to the receipt of the first command. The controller transmits a response of completion of data transfer. The first data and the second data are included in third data. The third data is data in the third memory.
    Type: Grant
    Filed: September 1, 2016
    Date of Patent: December 4, 2018
    Assignee: TOSHIBA MEMORY CORPORATION
    Inventors: Reina Nishino, Kenichi Maeda, Kenji Funaoka, Nobuhiro Kondo, Toshio Fujisawa
  • Publication number: 20180307632
    Abstract: According to one embodiment, a memory device includes a nonvolatile memory, a volatile memory, a controller, and a board. The nonvolatile memory stores data. The volatile memory holds a part of the data stored in the nonvolatile memory. The memory controller controls the volatile memory and the nonvolatile memory. The nonvolatile memory, the volatile memory, and the memory controller are provided on the board. The memory controller transmits an interrupt signal to a request source, when the volatile memory does not have any data corresponding to an address which the request source requests to access.
    Type: Application
    Filed: June 29, 2018
    Publication date: October 25, 2018
    Inventors: Toshio Fujisawa, Nobuhiro Kondo, Shoji Sawamura, Kenichi Maeda, Atsushi Kunimatsu