Patents by Inventor Kenichi Maeda
Kenichi Maeda has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 9870155Abstract: A device includes a host including a main memory, and semiconductor memory including a nonvolatile semiconductor memory, memory unit, and controller. The nonvolatile semiconductor memory stores first address information. The memory unit stores second address information as part of the first address information. The controller accesses the nonvolatile semiconductor memory based on the second address information. Third address information is stored in the main memory, and is part or all of the first address information. The controller uses the third address information when accessing the nonvolatile semiconductor memory if address information to be referred is not stored in the second address information.Type: GrantFiled: November 9, 2016Date of Patent: January 16, 2018Assignee: TOSHIBA MEMORY CORPORATIONInventors: Atsushi Kunimatsu, Kenichi Maeda
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Patent number: 9872090Abstract: 10-Gbps client signals (1a) to (1c) which are processed by a 10-Gbps transponder (3a), a 40-Gbps transponder (3b), and a 100-Gbps transponder (3c), respectively, are branched by optical couplers (2a) to (2c) into an M:N switch (40). The M:N switch (40) selects a client signal to be made redundant from the branched client signals (1a) to (1c) and outputs the selected client signal to a redundancy 100-Gbps transponder (50) having 10-Gbps-based client interfaces.Type: GrantFiled: January 6, 2015Date of Patent: January 16, 2018Assignee: MITSUBISHI ELECTRIC CORPORATIONInventor: Kenichi Maeda
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Patent number: 9864548Abstract: According to one embodiment, a memory module includes a volatile memory, a nonvolatile memory, and a controller. The volatile memory is data readable and writable. The nonvolatile memory is data readable and writable and stores therein correspondence information containing an attribute indicating any of volatile, nonvolatile, and both of volatile and nonvolatile associated with an address in an address space assigned to the volatile memory and the nonvolatile memory. The controller reads data from and writes data to the volatile memory or the nonvolatile memory, referring to the correspondence information.Type: GrantFiled: March 4, 2016Date of Patent: January 9, 2018Assignee: TOSHIBA MEMORY CORPORATIONInventors: Shoji Sawamura, Nobuhiro Kondo, Kenichi Maeda, Kenichiro Yoshii
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Publication number: 20170257298Abstract: According to one embodiment, a communication device 1 operating as a publisher calculates parity of a certain size which is capable of being commonly used for each of different data units from data to be sent each time receiving a lost notification from one or more communication device 1 operating as subscribers, the lost notification indicating that one or more data units are lost, and sends the calculated parity to the one or more communication devices 1 operating as the subscribers.Type: ApplicationFiled: September 7, 2016Publication date: September 7, 2017Applicant: Kabushiki Kaisha ToshibaInventors: Kenichi Maeda, Yujen Lai, Yosuke Bando, Hironori Uchikawa, Osamu Torii
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Publication number: 20170249102Abstract: According to one embodiment, an information processing apparatus includes a host device, a memory system and a power supply circuit. The host device includes a volatile first memory and a first control circuit. The memory system includes a non-volatile second memory in which user data is stored and a second control circuit. The second control circuit executes transfer of the user data between the host device and the second memory. The first memory includes an area used by the second control circuit. The second control circuit uses the area as a buffer for the transfer. The first control circuit causes the power supply circuit to start and stop the power supply to the memory system. The first control circuit accesses, while the power supply to the memory system is stopped, the buffer.Type: ApplicationFiled: September 7, 2016Publication date: August 31, 2017Applicant: Kabushiki Kaisha ToshibaInventors: Kenichi MAEDA, Kenji FUNAOKA, Reina NISHINO, Nobuhiro KONDO, Toshio FUJISAWA
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Publication number: 20170249247Abstract: According to one embodiment, a memory system is connectable to a host including a first memory. The memory system includes a non-volatile second memory, a volatile third memory, and a controller. The controller uses the third memory as a work memory, and executes data transfer between the host and the second memory. The controller receives a first command to change a power mode from the host. The controller transfers first data to the first memory and transfers second data to the second memory in response to the receipt of the first command. The controller transmits a response of completion of data transfer. The first data and the second data are included in third data. The third data is data in the third memory.Type: ApplicationFiled: September 1, 2016Publication date: August 31, 2017Applicant: Kabushiki Kaisha ToshibaInventors: Reina NISHINO, Kenichi MAEDA, Kenji FUNAOKA, Nobuhiro KONDO, Toshio FUJISAWA
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Publication number: 20170249167Abstract: According to one embodiment, the memory device includes a non-volatile memory, a volatile memory, and a controller. The controller carries out the transition to two different sleep states depending on a sleep instruction from the host device and saves sleep state information indicating the sleep state after the transition to the host-side storage device. Upon receiving a return instruction from the host device, the controller carries out return processing in accordance with the sleep state information stored in the host-side storage device.Type: ApplicationFiled: September 2, 2016Publication date: August 31, 2017Applicant: Kabushiki Kaisha ToshibaInventors: Yuji IZUMI, Kenichi MAEDA, Kenji FUNAOKA, Reina NISHINO, Toshio FUJISAWA, Nobuhiro KONDO
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Publication number: 20170180834Abstract: 10-Gbps client signals (1a) to (1c) which are processed by a 10-Gbps transponder (3a), a 40-Gbps transponder (3b), and a 100-Gbps transponder (3c), respectively, are branched by optical couplers (2a) to (2c) into an M:N switch (40). The M:N switch (40) selects a client signal to be made redundant from the branched client signals (1a) to (1c) and outputs the selected client signal to a redundancy 100-Gbps transponder (50) having 10-Gbps-based client interfaces.Type: ApplicationFiled: January 6, 2015Publication date: June 22, 2017Applicant: MITSUBISHI ELECTRIC CORPORATIONInventor: Kenichi MAEDA
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Publication number: 20170111819Abstract: According to one embodiment, a communication apparatus includes a congestion degree calculating unit and an operation mode setting unit. The congestion degree calculating unit calculates a third congestion degree related to wireless communication based on a first congestion degree of first wireless communication and a second congestion degree of second wireless communication. In the first wireless communication, peer-to-peer communication is performed directly between communication apparatuses, and in the second wireless communication, communication is performed through a wireless communication device. The operation mode setting unit switches an operation mode of the first wireless communication based on the third congestion degree to either of a mode in which the communication apparatus transmits content or a mode in which the communication apparatus receives content.Type: ApplicationFiled: March 1, 2016Publication date: April 20, 2017Applicant: Kabushiki Kaisha ToshibaInventors: Yosuke BANDO, Yujen LAI, Youyang NG, Kenichi MAEDA, Takeshi SAKODA, Takaomi MURAKAMI, Yusuke DOI, Masahiro ISHIYAMA
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Publication number: 20170075694Abstract: A memory system includes a memory and a command generator. The memory is connected to a host including a main memory and a processor connected to the main memory. The command generator generates an initialization command and transmits the initialization command to the host. The initialization command represents a command for instructing the initialization of the main memory and indicating an initialization method for the main memory.Type: ApplicationFiled: February 1, 2016Publication date: March 16, 2017Applicant: Kabushiki Kaisha ToshibaInventors: Nobuhiro KONDO, Kenichi MAEDA, Sven HEGNER
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Publication number: 20170078344Abstract: According to one embodiment, a communication apparatus includes a radio interface unit that sends a data message to a receiver and extracts, when a message sent by the receiver via unicast with an optimized transmission rate is received, rate information indicating the optimized transmission rate of the receiver from the received message, a message processor that generates the data message, in which a multicast identifier indicating a multicast group is a destination, and outputs the data message to the radio interface unit, and a selector that selects, according to the rate information, a data message transmission rate to send the data message.Type: ApplicationFiled: March 4, 2016Publication date: March 16, 2017Applicant: Kabushiki Kaisha ToshibaInventors: Yujen Lai, Yosuke Bando, Kenichi Maeda, Masahiro Ishiyama, Ren Sakata, Hiroki Kudo, Takeshi Sakoda
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Publication number: 20170075630Abstract: According to one embodiment, a memory module includes a volatile memory, a nonvolatile memory, and a controller. The volatile memory is data readable and writable. The nonvolatile memory is data readable and writable and stores therein correspondence information containing an attribute indicating any of volatile, nonvolatile, and both of volatile and nonvolatile associated with an address in an address space assigned to the volatile memory and the nonvolatile memory. The controller reads data from and writes data to the volatile memory or the nonvolatile memory, referring to the correspondence information.Type: ApplicationFiled: March 4, 2016Publication date: March 16, 2017Applicant: Kabushiki Kaisha ToshibaInventors: Shoji SAWAMURA, Nobuhiro Kondo, Kenichi Maeda, Kenichiro Yoshii
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Patent number: 9586613Abstract: A vehicle includes a pair of front wheels, a frame portion, a drive source, a pair of suspension assemblies, a pair of drive shafts, a steering wheel, and a transfer mechanism which transfers movement of the steering wheel to the pair of front wheels. Each of the pair of suspension assemblies includes an upper arm supported pivotably by the frame portion, a lower arm supported pivotably by the frame portion below the upper arm, and a knuckle arm connecting the upper arm and the lower arm to each other. The transfer mechanism includes a steering shaft portion extending from the steering wheel and rotates with the steering wheel, a rack-and-pinion portion provided at a tip region of the steering shaft portion, and a pair of tie rods extending in a width direction of the vehicle and connecting the rack-and-pinion portion to the pair of knuckle arms. Each of the pair of drive shafts passes through between the upper arm and the lower arm, whereas each of the pair of tie rods passes above the upper arm.Type: GrantFiled: February 12, 2014Date of Patent: March 7, 2017Assignee: YAMAHA HATSUDOKI KABUSHIKI KAISHAInventors: Masahide Shinbori, Kenichi Maeda
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Publication number: 20170060418Abstract: A device includes a host including a main memory, and semiconductor memory including a nonvolatile semiconductor memory, memory unit, and controller. The nonvolatile semiconductor memory stores first address information. The memory unit stores second address information as part of the first address information. The controller accesses the nonvolatile semiconductor memory based on the second address information. Third address information is stored in the main memory, and is part or all of the first address information. The controller uses the third address information when accessing the nonvolatile semiconductor memory if address information to be referred is not stored in the second address information.Type: ApplicationFiled: November 9, 2016Publication date: March 2, 2017Applicant: KABUSHIKI KAISHA TOSHIBAInventors: Atsushi KUNIMATSU, Kenichi MAEDA
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Publication number: 20170055272Abstract: According to one embodiment, a communication apparatus includes an operation mode storage unit that stores a mode in which the communication apparatus operates as a wireless base station or a terminal and a non-volatile memory, wherein a transmission message is output to the outside when the communication apparatus operates as the wireless base station, data included in a received reception message is stored in the non-volatile memory when the communication apparatus operates as the terminal, and when the communication apparatus operates as the wireless base station, after all data transmitted from a first external wireless base station is received, if a communication quality with the first wireless base station is less than a predetermined value, and no message is received from a wireless base station other than the first wireless base station, a channel selection and switching process is performed, and then the operation mode is changed from the terminal to the wireless base station.Type: ApplicationFiled: March 9, 2016Publication date: February 23, 2017Applicant: Kabushiki Kaisha ToshibaInventors: Yosuke BANDO, Hiroki KUDO, Masahiro ISHIYAMA, Kenichi MAEDA, Yujen LAI, Hiroto NAKAI
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Patent number: 9569303Abstract: According to one embodiment, an information processing apparatus includes a host and a memory system. The memory system includes a nonvolatile memory. The host includes a volatile memory, a first host control unit, and a second host control unit. The volatile memory includes a first area to be used by the host and a second area as a cache memory to temporarily store data of the nonvolatile memory. The first host control unit computes a first code, and stores the first data and the first code in the second area. The first code is redundant information of the first data. The second host control unit reads second data and a second code from the second area, performs error detection on the second data based on the second code, and transfers the second data. The second code is redundant information of the second data.Type: GrantFiled: February 27, 2015Date of Patent: February 14, 2017Assignee: Kabushiki Kaisha ToshibaInventors: Kenichi Maeda, Nobuhiro Kondo, Kenichiro Yoshii, Satoshi Kaburaki
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Patent number: 9542117Abstract: A device includes a host including a main memory, and semiconductor memory including a nonvolatile semiconductor memory, memory unit, and controller. The nonvolatile semiconductor memory stores first address information. The memory unit stores second address information as part of the first address information. The controller accesses the nonvolatile semiconductor memory based on the second address information. Third address information is stored in the main memory, and is part or all of the first address information. The controller uses the third address information when accessing the nonvolatile semiconductor memory if address information to be referred is not stored in the second address information.Type: GrantFiled: December 10, 2015Date of Patent: January 10, 2017Assignee: KABUSHIKI KAISHA TOSHIBAInventors: Atsushi Kunimatsu, Kenichi Maeda
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Patent number: 9524121Abstract: According to one embodiment, a memory device is connectable to a host device. The memory device includes a first interface unit, a controller unit, a second memory and a second interface. The first interface unit receives a write command from the host device. The controller unit acquires the write-data associated with the write command stored in a first memory area of a first memory in the host device, the write-data being copied from a second memory area of the first memory. The second interface causes the second memory to write the write-data in the second memory.Type: GrantFiled: February 4, 2013Date of Patent: December 20, 2016Assignee: Kabushiki Kaisha ToshibaInventors: Kenichi Maeda, Nobuhiro Kondo, Atsushi Kunimatsu
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Patent number: 9473317Abstract: According to the embodiments, a communication apparatus stores therein an operation mode indicating whether the communication apparatus is a publisher or a subscriber, and includes a message processing unit that generates a transmission message and analyzes a reception message and a nonvolatile memory. When the communication apparatus is subscriber, the communication apparatus sends a repair message to request a retransmission of a data chunk not successively received. When the communication apparatus is publisher, the communication apparatus selectively retransmits the data chunk based on the repair message.Type: GrantFiled: March 7, 2014Date of Patent: October 18, 2016Assignee: Kabushiki Kaisha ToshibaInventors: Arata Miyamoto, Kenichi Maeda, Masahiro Ishiyama, Hiroto Nakai
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Patent number: 9456316Abstract: A mode of a publisher or a subscriber is stored. Also, a first identifier indicating affiliation to a first group is stored. In a case of the publisher, a transmission message including ToC information, which is a list of the first identifiers and data to be transmitted, is transmitted to an outside. In a case of the subscriber, when a received message includes the first identifier, data included in the message is stored into a non-volatile memory, and when it is determined that all data in the ToC information stored in the received message are already received and that the number of publishers is less than a threshold, the stored mode is changed to the publisher.Type: GrantFiled: September 11, 2014Date of Patent: September 27, 2016Assignee: Kabushiki Kaisha ToshibaInventors: Masahiro Ishiyama, Arata Miyamoto, Kenichi Maeda, Hiroki Kudo, Hiroto Nakai