Patents by Inventor Kenichi Miyamoto
Kenichi Miyamoto has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20240363372Abstract: A substrate processing apparatus that can quickly transport a polished substrate (e.g., a wafer) to a cleaning module is disclosed. A first processing unit includes: a polishing module configured to polish the substrate W; a cleaning module configured to clean the substrate W; a drying module configured to dry the cleaned substrate W; a substrate transporter extending from one side to opposite side of the first processing unit; an elevating transporter configured to transport the substrate from the substrate transporter to the polishing module and from the polishing module to the cleaning module; and a relay transporter configured to transport the substrate. The relay transporter of the first processing unit is configured to transport the substrate between processing units.Type: ApplicationFiled: April 22, 2024Publication date: October 31, 2024Inventors: Mitsuru MIYAZAKI, Hiroshi SOTOZAKI, Hiroki MIYAMOTO, Kenichi TAKEBUCHI, Saki MIYAGAWA, Hiroki SAITO, Takuya INOUE, Shozo TAKAHASHI, Ryohei ISHII
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Patent number: 12097715Abstract: A thermal head includes a substrate, a bonding material, an electrically conductive member, and a gold electrode. The bonding material is located on the substrate and contains gold and tin. The electrically conductive member is located on the bonding material. The gold electrode is located on the substrate and electrically connected to the bonding material.Type: GrantFiled: March 26, 2021Date of Patent: September 24, 2024Assignee: KYOCERA CORPORATIONInventors: Kenichi Kato, Makoto Miyamoto
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Publication number: 20240290881Abstract: A drift layer is formed over a semiconductor substrate which is an SiC substrate. The drift layer includes first to third n-type semiconductor layers and a p-type impurity region. Herein, an impurity concentration of the second n-type semiconductor layer is higher than an impurity concentration of the first n-type semiconductor layer and an impurity concentration of the third n-type semiconductor layer. Also, in plan view, the second semiconductor layer located between the p-type impurity regions adjacent to each other overlaps with at least a part of a gate electrode formed in a trench.Type: ApplicationFiled: April 18, 2024Publication date: August 29, 2024Inventors: Yasuhiro OKAMOTO, Nobuo MACHIDA, Koichi ARAI, Kenichi HISADA, Yasunori YAMASHITA, Satoshi EGUCHI, Hironobu MIYAMOTO, Atsushi SAKAI, Katsumi EIKYU
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Patent number: 12049090Abstract: A thermal head includes a substrate, an electrode, a bonding material, an electrically conductive member, and a sealing material. The electrode is located on the substrate. The bonding material is located on the substrate or the electrode. The electrically conductive member is located on the bonding material and is electrically connected to the electrode via the bonding material. The sealing material is located on the substrate and covers the bonding material and the electrically conductive member. The bonding material includes a protruding portion located at an outer circumferential edge of the electrically conductive member away from the substrate and the electrically conductive member.Type: GrantFiled: March 26, 2021Date of Patent: July 30, 2024Assignee: KYOCERA CORPORATIONInventors: Kenichi Kato, Makoto Miyamoto
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Patent number: 12042823Abstract: An article sorting facility includes: a first floor including a plurality of first travel paths; a second floor installed at a different height from the first floor in a vertical direction, and including a plurality of second travel paths; a plurality of first elevation mechanisms connecting terminating ends of the first travel paths to starting ends of the second travel paths; a plurality of second elevation mechanisms connecting terminating ends of the second travel paths to starting ends of the first travel paths; a plurality of receiving sections configured to receive articles from the transport vehicles; and at least one supply section configured to supply the articles to the transport vehicles. The plurality of second travel paths overlap corresponding first travel paths or corresponding receiving sections as viewed in the vertical direction, at least in a partial segment.Type: GrantFiled: January 30, 2023Date of Patent: July 23, 2024Assignee: Daifuku Co., Ltd.Inventors: Yasuhisa Mishina, Tadasuke Ogawa, Kouji Fujita, Kenichi Ukisu, Nobuhiko Sato, Masaya Miyamoto
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Patent number: 11985792Abstract: An enclosure of an electronic computing apparatus allows two electronic computing modules, each having a built-in fan, to be mounted in a perpendicular direction, when the two electronic computing modules are inserted, a shutter is at an intermediate position due to an elastic force of pushing a spring cover in a front surface direction, from push rods corresponding to the two electronic computing modules, and when one of the electronic computing modules is removed, the elastic force of pushing the cover from the push rod on the removal is lost, and the shutter moves, around a rotating mechanism, to a side of a housing space on the removal side and shuts off a flow path in the housing space.Type: GrantFiled: March 7, 2022Date of Patent: May 14, 2024Assignee: HITACHI, LTD.Inventors: Sho Ikeda, Osamu Kamimura, Kenichi Miyamoto, Akihiro Adachi
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Publication number: 20230332674Abstract: A booster lever unit includes a first lever pivotably supported by an object via a first pivotal shaft, a second lever pivotably supported by the object via a second pivotal shaft, and a linkage member that links the first lever to the second lever. The pivotal plane of the first lever is parallel to the pivotal plane of the second lever. The first lever has one end provided with an operation section, and another end provided with the first pivotal shaft, and the first lever further includes a first linker, the first linker being provided between the operation section and the first pivotal shaft and linked to the linkage member. The second lever has one end provided with an action section, and another end provided with a second linker linked to the linkage member, and the second pivotal shaft is provided between the action section and the second linker.Type: ApplicationFiled: August 31, 2022Publication date: October 19, 2023Inventors: Sho IKEDA, Akihiro ADACHI, Osamu KAMIMURA, Kenichi MIYAMOTO, Yosuke ISHIDA
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Publication number: 20230171913Abstract: An enclosure of an electronic computing apparatus allows two electronic computing modules, each having a built-in fan, to be mounted in a perpendicular direction, when the two electronic computing modules are inserted, a shutter is at an intermediate position due to an elastic force of pushing a spring cover in a front surface direction, from push rods corresponding to the two electronic computing modules, and when one of the electronic computing modules is removed, the elastic force of pushing the cover from the push rod on the removal is lost, and the shutter moves, around a rotating mechanism, to a side of a housing space on the removal side and shuts off a flow path in the housing space.Type: ApplicationFiled: March 7, 2022Publication date: June 1, 2023Applicant: Hitachi, Ltd.Inventors: Sho IKEDA, Osamu KAMIMURA, Kenichi MIYAMOTO, Akihiro ADACHI
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Patent number: 10716218Abstract: A display device is provided with a laminated wiring including a low-resistance conductive film, a low-reflection film mainly containing Al and functioning as a reflection preventing film, and a cap film which are sequentially laminated on a transparent substrate, and an insulting film formed so as to cover the laminated wiring.Type: GrantFiled: March 8, 2013Date of Patent: July 14, 2020Assignee: Mitsubishi Electric CorporationInventors: Masami Hayashi, Kenichi Miyamoto, Nobuaki Ishiga, Kensuke Nagayama, Naoki Tsumura
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Patent number: 10656482Abstract: A channel layer is formed of an oxide semiconductor. A first insulating film is provided on the channel layer, a source line, and a drain electrode, and includes a drain contact hole which reaches the drain electrode. A pixel electrode is provided on the first insulating film, includes a connection conductive layer which is connected to the drain electrode by the drain contact hole, and is formed of a transparent conductive material. The pixel electrode is covered with a second insulating film. A common electrode is provided on the second insulating film, includes an opening which faces the pixel electrode in a thickness direction, and is formed of a transparent conductive material. A metal layer, in conjunction with a part of the common electrode, forms a laminated structure, and includes a light-shield part which overlaps the channel layer at least partially in plan view.Type: GrantFiled: May 8, 2017Date of Patent: May 19, 2020Assignee: Mitsubishi Electric CorporationInventors: Shinji Kawabuchi, Naruhito Hoka, Kazushi Yamayoshi, Akihiko Hosono, Kenichi Miyamoto
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Patent number: 10274854Abstract: A toner for developing an electrostatic charge image, the toner including: elemental iron, wherein a content of the elemental iron is in a range of 1.0×103 to 1.0×104 ppm, based on a total weight of the toner; elemental silicon, wherein a content of the elemental silicon is in a range of 1.0×103 to 5.0×103 ppm, based on a total weight of the toner; elemental sulfur, wherein a content of the elemental sulfur is in a range of 500 to 3,000 ppm, based on a total weight of the toner; optionally elemental fluorine, wherein a content of the elemental fluorine, if present, is in a range of 1.0×103 to 1.0×104 ppm; and a binder resin.Type: GrantFiled: August 21, 2017Date of Patent: April 30, 2019Assignee: Samsung Electronics Co., Ltd.Inventors: Masahide Yamada, Akinori Terada, Keiichi Ishikawa, Kenichi Miyamoto
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Patent number: 10234780Abstract: A toner for developing an electrostatic charge image includes three or more elements selected from a group including an iron element, a silicon element, a sulfur element and a fluorine element and a binder resin including an amorphous polyester-based resin.Type: GrantFiled: July 1, 2016Date of Patent: March 19, 2019Assignee: Samsung Electronics Co., Ltd.Inventors: Akinori Terada, Keiichi Ishikawa, Kenichi Miyamoto, Masahide Yamada
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Patent number: 10126665Abstract: A peripheral exposure method for performing an exposure treatment by illuminating light to a periphery of a resist film formed on a substrate to be processed is discussed. The method includes rotating the substrate to be processed on a horizontal plane, bringing a coolant gas into contact with the periphery of the resist film of the substrate to be processed which is being rotated, and cooling the substrate to be processed. Further, the method also includes measuring a temperature of the substrate to be processed, wherein when the temperature of the substrate to be processed is equal to or less than a predetermined temperature, the exposure treatment is performed.Type: GrantFiled: January 12, 2016Date of Patent: November 13, 2018Assignee: TOKYO ELECTRON LIMITEDInventors: Kenichi Miyamoto, Minoru Kubota
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Patent number: 10106685Abstract: A colored metallic pigment according to the present invention is a colored metallic pigment including at least a metallic pigment, an amorphous silicon oxide film layer formed on a surface of the metallic pigment, a metallic-particle-supporting layer formed on a surface of the amorphous silicon oxide film layer, and metallic particles formed on a surface of the metallic-particle-supporting layer, characterized in that the metallic-particle-supporting layer is formed of one or both of a metal layer and a metal oxide layer composed of a metal oxide other than silicon oxide, the metallic particles are formed to directly cover a part of the surface of the metallic-particle-supporting layer, and the amorphous silicon oxide film layer has a thickness of more than 500 nm.Type: GrantFiled: July 2, 2015Date of Patent: October 23, 2018Assignee: TOYO ALUMINIUM KABUSHIKI KAISHAInventors: Kenichi Miyamoto, Takayuki Nakao, Taro Morimitsu
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Patent number: 9910199Abstract: A display includes: a laminated wiring with a conductive film arranged on a foundation layer, and a transparent film and a translucent film arranged on the conductive film; a wiring terminal part arranged at an edge portion of the laminated wiring and having the same laminated structure as that of the laminated wiring; and an insulating film that covers the laminated wiring and the wiring terminal part.Type: GrantFiled: August 19, 2016Date of Patent: March 6, 2018Assignee: Mitsubishi Electric CorporationInventors: Masami Hayashi, Kenichi Miyamoto, Nobuaki Ishiga, Naoki Tsumura, Kensuke Nagayama
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Publication number: 20170351189Abstract: A toner for developing an electrostatic charge image, the toner including: elemental iron, wherein a content of the elemental iron is in a range of 1.0×103 to 1.0×104 ppm, based on a total weight of the toner; elemental silicon, wherein a content of the elemental silicon is in a range of 1.0×103 to 5.0×103 ppm, based on a total weight of the toner; elemental sulfur, wherein a content of the elemental sulfur is in a range of 500 to 3,000 ppm, based on a total weight of the toner; optionally elemental fluorine, wherein a content of the elemental fluorine, if present, is in a range of 1.0×103 to 1.Type: ApplicationFiled: August 21, 2017Publication date: December 7, 2017Applicant: SAMSUNG ELECTRONICS CO., LTD.Inventors: Masahide YAMADA, Akinori TERADA, Keiichi ISHIKAWA, Kenichi MIYAMOTO
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Publication number: 20170329176Abstract: A channel layer is formed of an oxide semiconductor. A first insulating film is provided on the channel layer, a source line, and a drain electrode, and includes a drain contact hole which reaches the drain electrode. A pixel electrode is provided on the first insulating film, includes a connection conductive layer which is connected to the drain electrode by the drain contact hole, and is formed of a transparent conductive material. The pixel electrode is covered with a second insulating film. A common electrode is provided on the second insulating film, includes an opening which faces the pixel electrode in a thickness direction, and is formed of a transparent conductive material. A metal layer, in conjunction with a part of the common electrode, forms a laminated structure, and includes a light-shield part which overlaps the channel layer at least partially in plan view.Type: ApplicationFiled: May 8, 2017Publication date: November 16, 2017Applicant: Mitsubishi Electric CorporationInventors: Shinji KAWABUCHI, Naruhito HOKA, Kazushi YAMAYOSHI, Akihiko HOSONO, Kenichi MIYAMOTO
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Patent number: D948504Type: GrantFiled: April 6, 2020Date of Patent: April 12, 2022Assignee: Hitachi, Ltd.Inventors: Shotaro Tamayama, Kenichi Miyamoto, Shinji Shibuya, Yoshikatsu Kasahara
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Patent number: D949850Type: GrantFiled: April 6, 2020Date of Patent: April 26, 2022Assignee: Hitachi, Ltd.Inventors: Shotaro Tamayama, Kenichi Miyamoto, Shinji Shibuya, Yoshikatsu Kasahara
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Patent number: D956734Type: GrantFiled: April 6, 2020Date of Patent: July 5, 2022Assignee: Hitachi, Ltd.Inventors: Shotaro Tamayama, Kenichi Miyamoto, Shinji Shibuya, Yoshikatsu Kasahara