Abstract: A plurality of semiconductor chips are provided on a base substrate. A drain region of the respective semiconductor chip is directly connected to the base substrate. A source electrode is formed in parallel with the arranging direction of the plurality of semiconductor chips. A source electrode and a source region of the respective semiconductor chip are connected using bonding wires. A plurality of source terminals are connected to the source electrode. A plurality of drain terminals are connected to the base substrate. The source terminal and drain terminal are located close to one another.

Abstract: A plurality of MOS transistors are arranged on the top surface of a conductor substrate which is a drain electrode. The drain contact of each MOS transistor is connected to the conductor substrate. The source contact of each MOS transistor is connected to the output conductor path which is a source electrode through a bonding wire. The gate contact of each MOS transistor is connected to a drive signal conductor path which is a gate electrode through a bonding wire. The source contacts of the MOS transistors are interconnected through a bridge electrode and a bonding wire.

Abstract: The side of one of the source electrodes 7a and 7b of two semiconductor modules Q1 and Q2 corresponding to a pair of upper and lower arms are installed parallel with the outer side of the other source electrode inside packages 8a and 8b. Both the modules are arranged parallel to one another in such a way that both the sides are opposed, an inter-module electrode terminal 15 for connecting the source electrode 7a of the module Q1 and the drain electrode (base substrate) 6b of the module Q2 is formed in a block shape, and one end of the inter-module electrode terminal 15 is vertically installed parallel and close to the side of the source electrode 7b on the base substrate of the module Q2.