Patents by Inventor Kenichi Suzaki
Kenichi Suzaki has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20110217852Abstract: Provided is technology for preventing breakage of an induction target part of a substrate processing apparatus using an induction heating method.Type: ApplicationFiled: March 3, 2011Publication date: September 8, 2011Applicant: HITACHI KOKUSAI ELECTRIC INC.Inventors: Kenichi SUZAKI, Takuya JODA
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Publication number: 20110131804Abstract: A support section (28) for supporting a wafer (1) is convexly formed in the center of a receiving section (26) of a support groove (25) of a boat 21. At the time of boat loading of the boat (21), in which wafers (1) respectively received by the supporting sections (28) are aligned, from a standby chamber (33) to a processing chamber (14), the pressure in the standby chamber (33) and processing chamber (14) is set to 200 pascals or more, and 3000 pascals or less. By supporting the wafer upwards from the receiving section with use of the support section, even if peeling of the film on the wafer occurs from a large frictional force between the supported surface of the wafer and the support section under a reduced pressure, the particles from the peeling are caught by the receiving section and therefore particles are prevented from adhering to the IC fabrication surface of the wafer directly below the receiving section.Type: ApplicationFiled: January 25, 2011Publication date: June 9, 2011Applicant: Hitachi Kokusai Electric Inc.Inventors: Takashi Ozaki, Kenichi Suzaki
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Patent number: 7955991Abstract: Disclosed is a producing method of a semiconductor device, comprising: loading a substrate into a reaction furnace; forming a film on the substrate in the reaction furnace; unloading the substrate from the reaction furnace after the film has been formed; and forcibly cooling an interior of the reaction furnace in a state where the substrate does not exist in the reaction furnace after the substrate has been unloaded.Type: GrantFiled: September 17, 2004Date of Patent: June 7, 2011Assignee: Hitachi Kokussai Electric Inc.Inventors: Kenichi Suzaki, Jie Wang
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Patent number: 7915165Abstract: A support section (28) for supporting a wafer (1) is convexly formed in the center of a receiving section (26) of a support groove (25) of a boat 21. At the time of boat loading of the boat (21), in which wafers (1) respectively received by the supporting sections (28) are aligned, from a standby chamber (33) to a processing chamber (14), the pressure in the standby chamber (33) and processing chamber (14) is set to 200 pascals or more, and 3000 pascals or less. By supporting the wafer upwards from the receiving section with use of the support section, even if peeling of the film on the wafer occurs from a large frictional force between the supported surface of the wafer and the support section under a reduced pressure, the particles from the peeling are caught by the receiving section and therefore particles are prevented from adhering to the IC fabrication surface of the wafer directly below the receiving section.Type: GrantFiled: April 14, 2010Date of Patent: March 29, 2011Assignee: Hitachi Kokusai Electric Inc.Inventors: Takashi Ozaki, Kenichi Suzaki
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Publication number: 20100201055Abstract: A support section (28) for supporting a wafer (1) is convexly formed in the center of a receiving section (26) of a support groove (25) of a boat 21. At the time of boat loading of the boat (21), in which wafers (1) respectively received by the supporting sections (28) are aligned, from a standby chamber (33) to a processing chamber (14), the pressure in the standby chamber (33) and processing chamber (14) is set to 200 pascals or more, and 3000 pascals or less. By supporting the wafer upwards from the receiving section with use of the support section, even if peeling of the film on the wafer occurs from a large frictional force between the supported surface of the wafer and the support section under a reduced pressure, the particles from the peeling are caught by the receiving section and therefore particles are prevented from adhering to the IC fabrication surface of the wafer directly below the receiving section.Type: ApplicationFiled: April 14, 2010Publication date: August 12, 2010Applicant: Hitachi Kokusai Electric Inc.Inventors: Takashi Ozaki, Kenichi Suzaki
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Patent number: 7737034Abstract: A support section (28) for supporting a wafer (1) is convexly formed in the center of a receiving section (26) of a support groove (25) of a boat 21. At the time of boat loading of the boat (21), in which wafers (1) respectively received by the supporting sections (28) are aligned, from a standby chamber (33) to a processing chamber (14), the pressure in the standby chamber (33) and processing chamber (14) is set to 200 pascals or more, and 3000 pascals or less. By supporting the wafer upwards from the receiving section with use of the support section, even if peeling of the film on the wafer occurs from a large frictional force between the supported surface of the wafer and the support section under a reduced pressure, the particles from the peeling are caught by the receiving section and therefore particles are prevented from adhering to the IC fabrication surface of the wafer directly below the receiving section.Type: GrantFiled: June 26, 2003Date of Patent: June 15, 2010Assignee: Hitachi Kokusai Electric Inc.Inventors: Takashi Ozaki, Kenichi Suzaki
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Patent number: 7731797Abstract: A gas flow in a load-lock type preliminary chamber is improved.Type: GrantFiled: October 26, 2005Date of Patent: June 8, 2010Assignee: Hitachi Kokusai Electric Inc.Inventors: Seiyo Nakashima, Tomoshi Taniyama, Kenichi Suzaki, Yoshikazu Takashima
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Publication number: 20090239386Abstract: Disclosed is a producing method of a semiconductor device, comprising: loading a substrate into a reaction furnace; forming a film on the substrate in the reaction furnace; unloading the substrate from the reaction furnace after the film has been formed; and forcibly cooling an interior of the reaction furnace in a state where the substrate does not exist in the reaction furnace after the substrate has been unloaded.Type: ApplicationFiled: March 16, 2009Publication date: September 24, 2009Inventors: Kenichi SUZAKI, Jie Wang
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Publication number: 20090205567Abstract: A process for producing a semiconductor device, in which in the formation of a boron doped silicon film from, for example, monosilane and boron trichloride by vacuum CVD technique, there can be produced a film excelling in inter-batch homogeneity with respect to the growth rate and concentration of a dopant element, such as boron. The process includes the step of performing the first purge through conducting at least once of while a substrate after treatment is housed in a reaction furnace, vacuuming of the reaction furnace and inert gas supply thereto and the steps of performing the second purge through conducting at least once of after carrying of the substrate after treatment out of the reaction furnace, prior to carrying of a substrate to be next treated into the reaction furnace and while at least no product substrate is housed in the reaction furnace, vacuuming of the reaction furnace and inert gas supply thereto.Type: ApplicationFiled: April 15, 2009Publication date: August 20, 2009Applicant: HITACHI KOKUSAI ELECTRIC INC.Inventors: Takaaki Noda, Kenichi Suzaki
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Publication number: 20090181523Abstract: A process for producing a semiconductor device, in which in the formation of a boron doped silicon film from, for example, monosilane and boron trichloride by vacuum CVD technique, there can be produced a film excelling in inter-batch homogeneity with respect to the growth rate and concentration of a dopant element, such as boron. The process includes the step of performing the first purge through conducting at least once of while a substrate after treatment is housed in a reaction furnace, vacuuming of the reaction furnace and inert gas supply thereto and the steps of performing the second purge through conducting at least once of after carrying of the substrate after treatment out of the reaction furnace, prior to carrying of a substrate to be next treated into the reaction furnace and while at least no product substrate is housed in the reaction furnace, vacuuming of the reaction furnace and inert gas supply thereto.Type: ApplicationFiled: March 12, 2009Publication date: July 16, 2009Applicant: HITACHI KOKUSAI ELECTRIC INC.Inventors: Takaaki Noda, Kenichi Suzaki
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Publication number: 20090181524Abstract: A process for producing a semiconductor device, in which in the formation of a boron doped silicon film from, for example, monosilane and boron trichloride by vacuum CVD technique, there can be produced a film excelling in inter-batch homogeneity with respect to the growth rate and concentration of a dopant element, such as boron. The process includes the step of performing the first purge through conducting at least once of while a substrate after treatment is housed in a reaction furnace, vacuuming of the reaction furnace and inert gas supply thereto and the steps of performing the second purge through conducting at least once of after carrying of the substrate after treatment out of the reaction furnace, prior to carrying of a substrate to be next treated into the reaction furnace and while at least no product substrate is housed in the reaction furnace, vacuuming of the reaction furnace and inert gas supply thereto.Type: ApplicationFiled: March 12, 2009Publication date: July 16, 2009Applicant: HITACHI KOKUSAI ELECTRIC INC.Inventors: Takaaki Noda, Kenichi Suzaki
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Patent number: 7556839Abstract: A process for producing a semiconductor device, in which in the formation of a boron doped silicon film from, for example, monosilane and boron trichloride by vacuum CVD technique, there can be produced a film excelling in inter-batch homogeneity with respect to the growth rate and concentration of a dopant element, such as boron. The process includes the step of performing the first purge through conducting at least once of while a substrate after treatment is housed in a reaction furnace, vacuuming of the reaction furnace and inert gas supply thereto and the steps of performing the second purge through conducting at least once of after carrying of the substrate after treatment out of the reaction furnace, prior to carrying of a substrate to be next treated into the reaction furnace and while at least no product substrate is housed in the reaction furnace, vacuuming of the reaction furnace and inert gas supply thereto.Type: GrantFiled: March 28, 2005Date of Patent: July 7, 2009Assignee: Hitachi Kokusai Electric Inc.Inventors: Takaaki Noda, Kenichi Suzaki
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Publication number: 20080268644Abstract: There are provided the steps of loading a substrate into a reaction vessel; forming a film on the substrate while supplying a film forming gas into the reaction vessel; unloading the substrate after film formation from the reaction vessel; supplying a cleaning gas into the reaction vessel while lowering a temperature in the reaction vessel and removing a deposit deposited on at least an inner wall of the reaction vessel in the film forming step.Type: ApplicationFiled: February 5, 2008Publication date: October 30, 2008Applicant: HITACHI KOKUSAI ELECTRIC INC.Inventors: Kenji Kameda, Naonori Akae, Kenichi Suzaki, Yushin Takasawa, Sadao Nakashima
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Publication number: 20080134977Abstract: A gas flow in a load-lock type preliminary chamber is improved.Type: ApplicationFiled: October 26, 2005Publication date: June 12, 2008Applicant: Hitachi Kokusai Electric Inc.Inventors: Seiyo Nakashima, Tomoshi Taniyama, Kenichi Suzaki, Yoshikazu Takashima
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Publication number: 20070259532Abstract: Disclosed is a producing method of a semiconductor device comprising: loading a substrate into a reaction furnace; forming a film on the substrate in the reaction furnace; unloading the substrate from the reaction furnace after the film has been formed, and forcibly cooling an interior of the reaction furnace in a state where the substrate does not exist in the reaction furnace after the substrate has been unloaded.Type: ApplicationFiled: September 17, 2004Publication date: November 8, 2007Applicant: HITACHI KOKUSAI ELECTRIC INC.Inventors: Kenichi Suzaki, Jie Wang
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Publication number: 20070178669Abstract: A process for producing a semiconductor device, in which in the formation of a boron doped silicon film from, for example, monosilane and boron trichloride by vacuum CVD technique, there can be produced a film excelling in inter-batch homogeneity with respect to the growth rate and concentration of a dopant element, such as boron. The process comprises the step of performing the first purge through conducting at least once of while a substrate after treatment is housed in a reaction furnace, vacuumizing of the reaction furnace and inert gas supply thereto and the steps (S38 to S44) of performing the second purge through conducting at least once of after carrying of the substrate after treatment out of the reaction furnace, prior to carrying of a substrate to be next treated into the reaction furnace and while at least no product substrate is housed in the reaction furnace, vacuumizing of the reaction furnace and inert gas supply thereto.Type: ApplicationFiled: March 28, 2005Publication date: August 2, 2007Applicant: HITACHI KOKUSALI ELECTRIC INC.Inventors: Takaaki Noda, Kenichi Suzaki
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Publication number: 20060205213Abstract: A support section (28) for supporting a wafer (1) is convexly formed in the center of a receiving section (26) of a support groove (25) of a boat 21. At the time of boat loading of the boat (21), in which wafers (1) respectively received by the supporting sections (28) are aligned, from a standby chamber (33) to a processing chamber (14), the pressure in the standby chamber (33) and processing chamber (14) is set to 200 pascals or more, and 3000 pascals or less. By supporting the wafer upwards from the receiving section with use of the support section, even if peeling of the film on the wafer occurs from a large frictional force between the supported surface of the wafer and the support section under a reduced pressure, the particles from the peeling are caught by the receiving section and therefore particles are prevented from adhering to the IC fabrication surface of the wafer directly below the receiving section.Type: ApplicationFiled: June 26, 2003Publication date: September 14, 2006Applicant: HITACHI KOKUSAI ELECTRIC INC.,Inventors: Takashi Ozaki, Kenichi Suzaki
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Patent number: 6790793Abstract: In a method for manufacturing a semiconductor device, the following three steps (oxide film forming step, cycle purge step, and coating step) are performed sequentially before performing substrates processing with a semiconductor device manufacturing apparatus. In the oxide film forming step, an oxide film 28 is grown on the surfaces of a flange portion 27 and a cap portion 30 which compose metal parts of a furnace port by baking the furnace port 40 so that corrosion resistance is improved. In the cycle purge step, residual moisture on the part of a gas supply system 35 and inside the piping is removed to suppress a chemical reaction between DCS gas which increases corrosiveness by reaction with moisture, and the metal parts 41 of the furnace port.Type: GrantFiled: February 28, 2003Date of Patent: September 14, 2004Assignee: Hitachi Kokusai Electric Inc.Inventors: Yutaka Nishino, Kenichi Suzaki, Norikazu Mizuno
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Patent number: 6720274Abstract: A semiconductor device fabricating method includes the steps of loading one or more substrates into a boat disposed in a waiting room positioned next to a reaction furnace; vacuum-evacuating the waiting room to a vacuum state at a base pressure; loading the boat into the reaction furnace at a first ambient pressure; and recovering a temperature of the reaction furnace at a second ambient pressure. The first or the second ambient pressure is greater than the vacuum state but less than the atmospheric pressure. Further, the method includes the step of increasing the temperature of the one or more substrates at a third ambient pressure, and also the third ambient pressure is greater than the base pressure but less than the atmospheric pressure.Type: GrantFiled: November 12, 2002Date of Patent: April 13, 2004Assignee: Hitachi Kokusai Electric Inc.Inventors: Takashi Ozaki, Kenichi Suzaki, Norikazu Mizuno
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Publication number: 20030224615Abstract: In a method for manufacturing a semiconductor device, the following three steps (oxide film forming step, cycle purge step, and coating step) are performed sequentially before performing substrates processing with a semiconductor device manufacturing apparatus. In the oxide film forming step, an oxide film 28 is grown on the surfaces of a flange portion 27 and a cap portion 30 which compose metal parts of a furnace port by baking the furnace port 40 so that corrosion resistance is improved. In the cycle purge step, residual moisture on the part of a gas supply system 35 and inside the piping is removed to suppress a chemical reaction between DCS gas which increases corrosiveness by reaction with moisture, and the metal parts 41 of the furnace port.Type: ApplicationFiled: February 28, 2003Publication date: December 4, 2003Applicant: HITACHI KOKUSAI ELECTRIC INC.Inventors: Yutaka Nishino, Kenichi Suzaki, Norikazu Mizuno