Patents by Inventor Kenichiro Toratani

Kenichiro Toratani has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 10964716
    Abstract: A semiconductor device comprises a substrate. A plurality of electrode layers and a plurality of insulating layers are formed in an alternating stack above the substrate. A semiconductor column extends through the plurality of electrode layers and the plurality of insulating layers. The semiconductor column comprises a single-crystal semiconductor material on an outer peripheral surface facing the electrode and insulating layers. First insulating films are formed between the semiconductor column and the electrode layers. The first insulating films are spaced from each other along the column length. Each first insulating film corresponds to one electrode layer. A charge storage layer is between each of the first insulating films and the electrode layers. A second insulating film is between the charge storage layer and each of the electrode layers.
    Type: Grant
    Filed: February 14, 2019
    Date of Patent: March 30, 2021
    Assignee: TOSHIBA MEMORY CORPORATION
    Inventors: Shinji Mori, Kazuhiro Matsuo, Yuta Saito, Keiichi Sawa, Kazuhisa Matsuda, Atsushi Takahashi, Masayuki Tanaka, Kenichiro Toratani
  • Patent number: 10910401
    Abstract: In one embodiment, a semiconductor device includes a substrate, insulating films and first films alternately stacked on the substrate, at least one of the first films including an electrode layer and a charge storage layer provided on a face of the electrode layer via a first insulator, and a semiconductor layer provided on a face of the charge storage layer via a second insulator. The device further includes at least one of a first portion including nitrogen and provided between the first insulator and the charge storage layer with an air gap provided in the first insulator, a second portion including nitrogen, provided between the charge storage layer and the second insulator, and including a portion protruding toward the charge storage layer, and a third portion including nitrogen and provided between the second insulator and the semiconductor layer with an air gap provided in the first insulator.
    Type: Grant
    Filed: September 3, 2019
    Date of Patent: February 2, 2021
    Assignee: TOSHIBA MEMORY CORPORATION
    Inventors: Keiichi Sawa, Kazuhiro Matsuo, Kazuhisa Matsuda, Hiroyuki Yamashita, Yuta Saito, Shinji Mori, Masayuki Tanaka, Kenichiro Toratani, Atsushi Takahashi, Shouji Honda
  • Publication number: 20200295035
    Abstract: In one embodiment, a semiconductor device includes a substrate, insulating films and first films alternately stacked on the substrate, at least one of the first films including an electrode layer and a charge storage layer provided on a face of the electrode layer via a first insulator, and a semiconductor layer provided on a face of the charge storage layer via a second insulator. The device further includes at least one of a first portion including nitrogen and provided between the first insulator and the charge storage layer with an air gap provided in the first insulator, a second portion including nitrogen, provided between the charge storage layer and the second insulator, and including a portion protruding toward the charge storage layer, and a third portion including nitrogen and provided between the second insulator and the semiconductor layer with an air gap provided in the first insulator.
    Type: Application
    Filed: September 3, 2019
    Publication date: September 17, 2020
    Applicant: TOSHIBA MEMORY CORPORATION
    Inventors: Keiichi SAWA, Kazuhiro MATSUO, Kazuhisa MATSUDA, Hiroyuki YAMASHITA, Yuta SAITO, Shinji MORI, Masayuki TANAKA, Kenichiro TORATANI, Atsushi TAKAHASHI, Shouji HONDA
  • Publication number: 20200091172
    Abstract: A semiconductor device comprises a substrate. A plurality of electrode layers and a plurality of insulating layers are formed in an alternating stack above the substrate. A semiconductor column extends through the plurality of electrode layers and the plurality of insulating layers. The semiconductor column comprises a single-crystal semiconductor material on an outer peripheral surface facing the electrode and insulating layers. First insulating films are formed between the semiconductor column and the electrode layers. The first insulating films are spaced from each other along the column length. Each first insulating film corresponds to one electrode layer. A charge storage layer is between each of the first insulating films and the electrode layers. A second insulating film is between the charge storage layer and each of the electrode layers.
    Type: Application
    Filed: February 14, 2019
    Publication date: March 19, 2020
    Inventors: Shinji MORI, Kazuhiro MATSUO, Yuta SAITO, Keiichi SAWA, Kazuhisa MATSUDA, Atsushi TAKAHASHI, Masayuki TANAKA, Kenichiro TORATANI
  • Patent number: 10593542
    Abstract: According to an embodiment, a manufacturing method of a semiconductor device includes: carrying a substrate alternately stacked an electrode layer and an insulation layer into a chamber; increasing the temperature in the chamber to a predetermined temperature; and supplying hydrogen and material gas including metal simultaneously into the chamber, and supplying oxidizing gas the partial pressure ratio of which to the hydrogen is set so as to provide an atmosphere of reducing the electrode layer, by using an ALD method, and thereby forming, on a surface of the electrode layer and a surface of the insulation layer, a metal oxide layer obtained by oxidizing the metal.
    Type: Grant
    Filed: September 5, 2017
    Date of Patent: March 17, 2020
    Assignee: TOSHIBA MEMORY CORPORATION
    Inventors: Takashi Furuhashi, Masayuki Tanaka, Shinji Mori, Kenichiro Toratani
  • Patent number: 10522596
    Abstract: In one embodiment, a semiconductor storage device includes a first interconnect extending in a first direction, a plurality of second interconnects extending in a second direction different from the first direction, and a plurality of first insulators provided alternately with the second interconnects. The device further includes a resistance change film provided between the first interconnect and at least one of the second interconnects and including a first metal layer or a first semiconductor layer that includes a first face provided on a first interconnect side and a second face provided on a second interconnect side, at least any of the first face and the second face having a curved plane shape.
    Type: Grant
    Filed: February 8, 2018
    Date of Patent: December 31, 2019
    Assignee: TOSHIBA MEMORY CORPORATION
    Inventors: Keiichi Sawa, Kazuhisa Matsuda, Atsushi Takahashi, Takaumi Morita, Masayuki Tanaka, Shinji Mori, Kazuhiro Matsuo, Yuta Saito, Kenichiro Toratani, Hisashi Okuchi
  • Patent number: 10396280
    Abstract: A semiconductor memory device includes a plurality of first interconnections extending in a first direction, and a second interconnection extending in a second direction different from the first direction. The device further includes a resistance change film provided between the plurality of first interconnections and the second interconnection, the resistance change film including (a) silicon and a semiconductor layer including one or more elements selected from among oxygen, carbon, nitrogen, phosphorus, boron, and germanium, or (b) a first layer containing the germanium and a second layer containing the silicon.
    Type: Grant
    Filed: September 5, 2017
    Date of Patent: August 27, 2019
    Assignee: Toshiba Memory Corporation
    Inventors: Shinji Mori, Masayuki Tanaka, Kazuhiro Matsuo, Kenichiro Toratani, Keiichi Sawa, Kazuhisa Matsuda, Atsushi Takahashi, Yuta Saito
  • Patent number: 10304850
    Abstract: A semiconductor memory device according to an embodiment includes a substrate, a stacked body provided on the substrate, a plurality of electrode films being stacked to be separated from each other in the stacked body, a semiconductor pillar piercing the plurality of electrode films, a first insulating film provided between the semiconductor pillar and the electrode films, a second insulating film provided between the semiconductor pillar and the first insulating film; and a third insulating film provided between the first insulating film and the electrode films. The first insulating film includes silicon, nitrogen, oxygen, and carbon.
    Type: Grant
    Filed: February 1, 2016
    Date of Patent: May 28, 2019
    Assignee: Toshiba Memory Corporation
    Inventors: Kazuhiro Matsuo, Masayuki Tanaka, Shinji Mori, Kenichiro Toratani
  • Patent number: 10283646
    Abstract: According to one embodiment, a nonvolatile semiconductor memory device includes first and second gate electrode layers, an inter-layer insulating layer, a channel layer, a tunneling insulating layer, first and second charge storage portions, and a blocking insulating layer. The channel layer is separated from the first and second gate electrode layers, and the inter-layer insulating layer. The tunneling insulating layer is provided between the first gate electrode layer and the channel layer. The first charge storage portion is provided between the first gate electrode layer and the tunneling insulating layer. The second charge storage portion is provided the second gate electrode layer and the tunneling insulating layer. The blocking insulating layer is provided between the inter-layer insulating layer and the tunneling insulating layer, between the first gate electrode layer and the first charge storage portion, between the inter-layer insulating layer and the first charge storage portion.
    Type: Grant
    Filed: March 9, 2017
    Date of Patent: May 7, 2019
    Assignee: Toshiba Memory Corporation
    Inventors: Keiichi Sawa, Shinji Mori, Masayuki Tanaka, Kenichiro Toratani, Takashi Furuhashi
  • Publication number: 20190027538
    Abstract: In one embodiment, a semiconductor storage device includes a first interconnect extending in a first direction, a plurality of second interconnects extending in a second direction different from the first direction, and a plurality of first insulators provided alternately with the second interconnects. The device further includes a resistance change film provided between the first interconnect and at least one of the second interconnects and including a first metal layer or a first semiconductor layer that includes a first face provided on a first interconnect side and a second face provided on a second interconnect side, at least any of the first face and the second face having a curved plane shape.
    Type: Application
    Filed: February 8, 2018
    Publication date: January 24, 2019
    Applicant: TOSHIBA MEMORY CORPORATION
    Inventors: Keiichi Sawa, Kazuhisa Matsuda, Atsushi Takahashi, Takaumi Morita, Masayuki Tanaka, Shinji Mori, Kazuhiro Matsuo, Yuta Saito, Kenichiro Toratani, Hisashi Okuchi
  • Publication number: 20180277757
    Abstract: A semiconductor memory device includes a plurality of first interconnections extending in a first direction, and a second interconnection extending in a second direction different from the first direction. The device further includes a resistance change film provided between the plurality of first interconnections and the second interconnection, the resistance change film including(a) silicon and a semiconductor layer including one or more elements selected from among oxygen, carbon, nitrogen, phosphorus, boron, and germanium, or (b) a first layer containing the germanium and a second layer containing the silicon.
    Type: Application
    Filed: September 5, 2017
    Publication date: September 27, 2018
    Applicant: TOSHIBA MEMORY CORPORATION
    Inventors: Shinji MORI, Masayuki TANAKA, Kazuhiro MATSUO, Kenichiro TORATANI, Keiichi SAWA, Kazuhisa MATSUDA, Atsushi TAKAHASHI, Yuta SAITO
  • Publication number: 20180261445
    Abstract: According to an embodiment, a manufacturing method of a semiconductor device includes: carrying a substrate alternately stacked an electrode layer and an insulation layer into a chamber; increasing the temperature in the chamber to a predetermined temperature; and supplying hydrogen and material gas including metal simultaneously into the chamber, and supplying oxidizing gas the partial pressure ratio of which to the hydrogen is set so as to provide an atmosphere of reducing the electrode layer, by using an ALD method, and thereby forming, on a surface of the electrode layer and a surface of the insulation layer, a metal oxide layer obtained by oxidizing the metal.
    Type: Application
    Filed: September 5, 2017
    Publication date: September 13, 2018
    Applicant: TOSHIBA MEMORY CORPORATION
    Inventors: Takashi FURUHASHI, Masayuki Tanaka, Shinji Mori, Kenichiro Toratani
  • Patent number: 9935122
    Abstract: A nonvolatile semiconductor memory device according to an embodiment comprises a memory cell, the memory cell comprising: a semiconductor layer; a control gate electrode; a charge accumulation layer disposed between the semiconductor layer and the control gate electrode; a first insulating layer disposed between the semiconductor layer and the charge accumulation layer; and a second insulating layer disposed between the charge accumulation layer and the control gate electrode, the charge accumulation layer including an insulator that includes silicon and nitrogen, and the insulator further including: a first element or a second element, the second element being different from the first element; and a third element different from the first element and the second element.
    Type: Grant
    Filed: March 16, 2016
    Date of Patent: April 3, 2018
    Assignee: TOSHIBA MEMORY CORPORATION
    Inventors: Tsunehiro Ino, Daisuke Matsushita, Yasushi Nakasaki, Misako Morota, Akira Takashima, Kenichiro Toratani
  • Publication number: 20170263640
    Abstract: According to one embodiment, a nonvolatile semiconductor memory device includes a semiconductor layer, a first electrode, first to third layers, and nitride portions of nitride molecules. The first layer is provided between the semiconductor layer and the first electrode. The second layer is provided between the first layer and the first electrode. The second energy of a conduction band edge of the second layer is lower than a first energy of a conduction band edge of the first layer. The second layer includes a first region and a second region. The first region is provided between the first layer and the second region. The third layer is provided between the second layer and the first electrode. The third energy of a conduction band edge of the third layer is higher than the second energy.
    Type: Application
    Filed: March 10, 2017
    Publication date: September 14, 2017
    Applicant: KABUSHIKI KAISHA TOSHIBA
    Inventors: Akira TAKASHIMA, Kenichiro Toratani, Masayuki Tanaka
  • Patent number: 9627402
    Abstract: A semiconductor memory device according to an embodiment, includes a stacked body, a semiconductor member, a charge storage layer, a charge block layer and an electrode antioxidant layer. The stacked body includes a plurality of electrode layers stacked separated from each other and an inter-electrode insulating layer between the electrode layers. The semiconductor member extends in a stacking direction of the stacked body and penetrates the stacked body. The tunnel insulating layer is provided on a side surface of the semiconductor member. The charge storage layer is provided on a side surface of the tunnel insulating layer. The charge block layer is provided on a side surface of the charge storage layer and contains oxygen. The electrode antioxidant layer is provided between the charge block layer and the electrode layer and has a composition different from that of the electrode layer.
    Type: Grant
    Filed: June 25, 2015
    Date of Patent: April 18, 2017
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Takashi Furuhashi, Masayuki Tanaka, Kenichiro Toratani
  • Publication number: 20170077115
    Abstract: A nonvolatile semiconductor memory device according to an embodiment comprises a memory cell, the memory cell comprising: a semiconductor layer; a control gate electrode; a charge accumulation layer disposed between the semiconductor layer and the control gate electrode; a first insulating layer disposed between the semiconductor layer and the charge accumulation layer; and a second insulating layer disposed between the charge accumulation layer and the control gate electrode, the charge accumulation layer including an insulator that includes silicon and nitrogen, and the insulator further including: a first element or a second element, the second element being different from the first element; and a third element different from the first element and the second element.
    Type: Application
    Filed: March 16, 2016
    Publication date: March 16, 2017
    Applicant: Kabushiki Kaisha Toshiba
    Inventors: Tsunehiro INO, Daisuke MATSUSHITA, Yasushi NAKASAKI, Misako MOROTA, Akira TAKASHIMA, Kenichiro TORATANI
  • Publication number: 20170069654
    Abstract: A semiconductor memory device according to an embodiment includes a substrate, a stacked body provided on the substrate, a plurality of electrode films being stacked to be separated from each other in the stacked body, a semiconductor pillar piercing the plurality of electrode films, a first insulating film provided between the semiconductor pillar and the electrode films, a second insulating film provided between the semiconductor pillar and the first insulating film; and a third insulating film provided between the first insulating film and the electrode films. The first insulating film includes silicon, nitrogen, oxygen, and carbon.
    Type: Application
    Filed: February 1, 2016
    Publication date: March 9, 2017
    Applicant: Kabushiki Kaisha Toshiba
    Inventors: Kazuhiro MATSUO, Masayuki TANAKA, Shinji Mori, Kenichiro Toratani
  • Patent number: 9590078
    Abstract: A semiconductor device fabrication method includes forming a tunnel insulating film on a substrate containing silicon, forming a floating gate on the tunnel insulating film, forming an integral insulating film on the floating gate, and forming a control gate on the integral insulating film. The floating gate is formed on the tunnel insulating film by forming a seed layer containing amorphous silicon on the tunnel insulating film, forming an impurity later containing adsorbed boron or germanium on the seed layer, and forming a cap layer containing silicon on the impurity layer.
    Type: Grant
    Filed: March 4, 2013
    Date of Patent: March 7, 2017
    Assignee: KABUSHIKI KAISHA TOSHIBA
    Inventors: Hirokazu Ishida, Kenichiro Toratani
  • Patent number: 9566620
    Abstract: An LPCVD apparatus is provided with a processing chamber and a reaction cooling apparatus. The reaction cooling apparatus is placed outside the processing chamber and is configured to generate hydrogen fluoride gas by reaction of hydrogen gas and fluorine gas and to cool the hydrogen fluoride gas. The hydrogen fluoride gas cooled by the reaction cooling apparatus is supplied into the processing chamber as a cleaning gas.
    Type: Grant
    Filed: August 6, 2013
    Date of Patent: February 14, 2017
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Kenichiro Toratani, Fumiki Aiso, Takashi Nakao, Kazuhei Yoshinaga
  • Patent number: 9478670
    Abstract: A non-volatile semiconductor storage device disclosed in the embodiment has a semiconductor substrate, a first insulating film, a first charge storage film, a second insulating film, a second charge storage film, a third insulating film, and a control electrode. In this non-volatile semiconductor storage device, the first and second charge storage films comprise a metallic material, a semi-metallic material or a semiconductor material. One of the first, second, and third insulating films is a multi-layered insulating film formed by layering multiple insulating films. This non-volatile semiconductor storage device further has a film comprising of any one of an oxide film, nitride film, boride film, sulfide film, and carbide film that is in contact with one interface of the laminated insulating film and contains one type of atom selected from aluminum, boron, alkaline earth metal, and transition metal at a concentration in the range of 1E12 atoms/cm2 to 1E16 atoms/cm2.
    Type: Grant
    Filed: July 8, 2013
    Date of Patent: October 25, 2016
    Assignee: KABUSHIKI KAISHA TOSHIBA
    Inventors: Masayuki Tanaka, Kenichiro Toratani