Abstract: A non-volatile semiconductor storage device includes: a memory cell array having memory cells arranged therein, the memory cells storing data in a non-volatile manner; and a plurality of transfer transistors transferring a voltage to the memory cells, the voltage to be supplied for data read, write and erase operations with respect to the memory cells. Each of the transfer transistors includes: a gate electrode formed on a semiconductor substrate via a gate insulation film; and diffusion layers formed to sandwich the gate electrode therebetween and functioning as drain/source layers. Upper layer wirings are provided above the diffusion layers and provided with a predetermined voltage to prevent depletion of the diffusion layers at least when the transfer transistors become conductive.

Abstract: A method of manufacturing a semiconductor device, comprising: forming, on a semiconductor substrate a gate insulating film for a high-voltage transistor of a peripheral circuit; forming on the gate insulating film a gate electrode for the high-voltage transistor; removing the gate insulating film positioned on the semiconductor substrate on both side portions of the gate electrode; forming an impurity diffusion region in a surface of the semiconductor substrate; depositing a first silicon oxide film to extend over surfaces of the gate electrode and the impurity diffusion region; etching the first silicon oxide film to form a spacer such that the spacer is formed on a side wall portion of the gate electrode and also extends over the surface of the semiconductor substrate; and forming a silicon nitride film on a surface of the spacer.

Abstract: A plurality of first transistors formed on a substrate share a gate electrode. Isolation regions isolate the plurality of first transistors from one another. In the region where the plurality of first transistors, an impurity region is formed in such a manner that it includes the source and drain regions of the plurality of first transistors and that the depth of the impurity region is greater than the depth of the source and drain regions. The impurity region sets the threshold voltage of the first transistors.

Abstract: A semiconductor device includes MOS transistors, capacitor elements, a voltage generating circuit, a contact plug, and a memory cell. The MOS transistor and the capacitor element are formed on a first one of the element regions and a second one of the element regions, respectively. In the voltage generating circuit, current paths of the MOS transistors are series-connected and the capacitor elements are connected to the source or drain of the MOS transistors. The contact plug is formed on the source or the drain to connect the MOS transistors or one of the MOS transistors and one of the capacitor elements. A distance between the gate and the contact plug both for a first one of the MOS transistors located in the final stage in the series connection is larger than that for a second one of the MOS transistors located in the initial stage in the series connection.

Abstract: A semiconductor memory device includes a first transistor. The first transistor includes a gate electrode, a channel region, a source region, a source region, an overlapping region, a contact region, and an impurity diffusion region. The channel region has a first impurity concentration. The source and drain regions have a second impurity concentration. The overlapping region is formed in the semiconductor layer where the channel region overlaps the source region and the drain region, and has a third impurity concentration. The contact region has a fourth impurity concentration. The impurity diffusion region has a fifth impurity concentration higher than the second impurity concentration and lower than the fourth impurity concentration. The impurity diffusion region is in contact with the contact region and away from the overlapping region and positioned at least in a region between the contact region and the overlapping region.

Abstract: A peripheral circuit area is formed around a memory cell array area. The peripheral circuit area has element regions, an element isolation region isolating the element regions, and field-effect transistor formed in each of the element regions and including a gate electrode extending in a channel width direction, on a semiconductor substrate. An end portion and a corner portion of the gate electrode are on the element isolation region. A radius of curvature of the corner portion of the gate electrode is smaller than a length from the end portion of the element region in the channel width direction to the end portion of the gate electrode in the channel width direction, and is less than 85 nm.

Abstract: A semiconductor memory device includes a memory cell block. The memory cell block includes a plurality of n-type first MIS transistors with current passages connected in series. Each of the first MIS transistors includes a source, a drain, and a charge storage layer formed on a (001)-plane of a semiconductor substrate with a gate insulating film interposed therebetween and is configured to store data. A direction from the source to the drain in each of the first MIS transistors is set parallel to a [001]-direction or [010]-direction of the semiconductor substrate.

Abstract: A memory includes a first word line which is connected to a control gate electrode of a first memory cell, a second word line which is connected to a control gate electrode of a second memory cell, a potential transfer line which is connected to both of the first and second word lines, a first N-channel MOS transistor which is connected between the first word line and the potential transfer line, and a second N-channel MOS transistor which is connected between the second word line and the potential transfer line. A control circuit supplies a first potential with a plus value to a semiconductor substrate, and supplies a second potential with the plus value lower than the first potential to the potential transfer line, to turn the first N-channel MOS transistor on, and to turn the second N-channel MOS transistor off, in erasing data of the first memory cell.

Abstract: A semiconductor memory device includes a memory cell string provided on a semiconductor substrate, and a first select transistor including a gate insulation film, which is provided on the semiconductor substrate having a recess structure which is lower, only at a central portion thereof, than the semiconductor substrate on which the memory cell string is provided, and a gate electrode provided on the gate insulation film, the first select transistor selecting the memory cell string.

Abstract: A first select transistor is connected to one end of a plurality of memory cell transistors that are serially connected. A second select transistor is connected to the other end of the serially connected memory cell transistors. A first impurity diffusion region is formed in a semiconductor substrate and constitutes a first main electrode of the first select transistor. A second impurity diffusion region is formed in the semiconductor substrate and constitutes a second main electrode of the second select transistor. A depth of the first impurity diffusion region is greater than a depth of the second impurity diffusion region.

Abstract: A peripheral circuit includes at least a first transistor. The first transistor comprises a gate electrode formed on a surface of a semiconductor layer via a gate insulating film. A channel region of a first conductivity type having a first impurity concentration is formed on a surface of the semiconductor layer directly below and in the vicinity of the gate electrode. A source-drain diffusion region of the first conductivity type is formed on the surface of the semiconductor layer to sandwich the gate electrode and has a second impurity concentration greater than the first impurity concentration. An overlapping region of the first conductivity type is formed on the surface of the semiconductor layer directly below the gate electrode where the channel region and the source-drain diffusion region overlap. The overlapping region has a third impurity concentration greater than the second impurity concentration.

Abstract: A non-volatile semiconductor storage device includes: a memory cell array having memory cells arranged therein, the memory cells storing data in a non-volatile manner; and a plurality of transfer transistors transferring a voltage to the memory cells, the voltage to be supplied for data read, write and erase operations with respect to the memory cells. Each of the transfer transistors includes: a gate electrode formed on a semiconductor substrate via a gate insulation film; and diffusion layers formed to sandwich the gate electrode therebetween and functioning as drain/source layers. Upper layer wirings are provided above the diffusion layers and provided with a predetermined voltage to prevent depletion of the diffusion layers at least when the transfer transistors become conductive.

Abstract: A semiconductor device includes MOS transistors, capacitor elements, a voltage generating circuit, a contact plug, and a memory cell. The MOS transistor and the capacitor element are formed on a first one of the element regions and a second one of the element regions, respectively. In the voltage generating circuit, current paths of the MOS transistors are series-connected and the capacitor elements are connected to the source or drain of the MOS transistors. The contact plug is formed on the source or the drain to connect the MOS transistors or one of the MOS transistors and one of the capacitor elements. A distance between the gate and the contact plug both for a first one of the MOS transistors located in the final stage in the series connection is larger than that for a second one of the MOS transistors located in the initial stage in the series connection.

Abstract: A memory cell includes a floating gate electrode, a first inter-electrode insulating film and a control gate electrode. A peripheral transistor includes a lower electrode, a second inter-electrode insulating film and an upper electrode. The lower electrode and the upper electrode are electrically connected via an opening provided on the second inter-electrode insulating film. The first and second inter-electrode insulating films include a high-permittivity material, the first inter-electrode insulating film has a first structure, and the second inter-electrode insulating film has a second structure different from the first structure.

Abstract: A semiconductor memory device includes a memory cell string provided on a semiconductor substrate, and a first select transistor including a gate insulation film, which is provided on the semiconductor substrate having a recess structure which is lower, only at a central portion thereof, than the semiconductor substrate on which the memory cell string is provided, and a gate electrode provided on the gate insulation film, the first select transistor selecting the memory cell string.

Abstract: A semiconductor memory device includes a memory cell block. The memory cell block includes a plurality of n-type first MIS transistors with current passages connected in series. Each of the first MIS transistors includes a source, a drain, and a charge storage layer formed on a (001)-plane of a semiconductor substrate with a gate insulating film interposed therebetween and is configured to store data. A direction from the source to the drain in each of the first MIS transistors is set parallel to a [001]-direction or [010]-direction of the semiconductor substrate.

Abstract: A plurality of first transistors formed on a substrate share a gate electrode. Isolation regions isolate the plurality of first transistors from one another. In the region where the plurality of first transistors, an impurity region is formed in such a manner that it includes the source and drain regions of the plurality of first transistors and that the depth of the impurity region is greater than the depth of the source and drain regions. The impurity region sets the threshold voltage of the first transistors.