Abstract: A semiconductor device is a semiconductor device in which a transistor is formed on a semiconductor substrate including a first main surface and a second main surface, a transistor region of the semiconductor substrate includes an n-type first semiconductor layer, a p-type second semiconductor layer provided closer to the first main surface than the first semiconductor layer, an n-type third semiconductor layer provided closer to a first main surface side than the second semiconductor layer, a trench gate that penetrates the third semiconductor layer and the second semiconductor layer in a thickness direction from the first main surface and reaches an inside of the first semiconductor layer, and an interlayer insulating film provided on the trench gate. The interlayer insulating film includes at least one narrow width portion in which a length in a width direction intersecting an extending direction of the trench gate in planar view is partially narrowed.

Abstract: A power conversion apparatus includes a hermetic housing, a power semiconductor module, and dry gas. The hermetic housing includes a gas inlet valve and a gas outlet valve. The power semiconductor module is arranged in an internal space in the hermetic housing. The internal space in the hermetic housing is filled with dry gas.

Abstract: Using an apparatus for manufacturing a thin steel sheet including the followings which are arranged in order: a continuous casting machine (1) for a thin slab having a slab thickness of 70 mm to 120 mm at a lower end of a mold; a holding furnace (2) that is configured to maintain a temperature of a cast slab (10) and/or heats the cast slab (10); and a rolling stand (3) by which finish rolling is performed, the casting speed of the thin slab is set to 4 to 7 m/min, the slab (10) is reduced at a rolling reduction of 30% or more by the reduction roll (4) after solidification is completed and when a center temperature of the slab is 1300° C. or higher, and the slab (10) is held at a temperature of 1150° C. or higher and 1300° C. or lower for five minutes or longer in the holding furnace (2).

Abstract: According to one embodiment, a display device includes a substrate, first and second insulating layers, first and second pixel electrodes, first and second organic layers, first and second feed lines, first and second partitions, and a common electrode including first and second parts covering the first and second organic layers. The first organic layer is between the partitions. The second feed line and the second partition are located between the organic layers. The partitions are shaped such that a width of an upper part is greater than a width of a lower part. The first part is in contact with the first feed line between the first partition and the first organic layer.

Abstract: An electric lock control method includes: performing a first determination of whether a person is present in a predetermined region surrounding an electric lock, based on first information generated by an electronic device; when it is determined that a first person is present in the predetermined region in the performing of the first determination, performing a second determination of whether the first person is a person who is permitted to unlock the electric lock, based on second information related to movement of the first person; and controlling a state of the electric lock based on a result of the second determination, the state being a locked state or an unlocked state.

Abstract: A soft magnetic alloy or the like combines high saturated magnetic flux density, low coercive force and high magnetic permeability ??. A soft magnetic alloy having the composition formula (Fe(1?(?+?))X1?X2?)(1?(a+b+c+d+e))BaSibCcCudMe. X1 is one or more elements selected from the group consisting of Co and Ni, X2 is one or more elements selected from the group consisting of Al, Mn, Ag, Zn, Sn, As, Sb, Bi, N, O and rare earth elements, and M is one or more elements selected from the group consisting of Nb, Hf, Zr, Ta, Ti, Mo, ?? and V. 0.090?a?0.240, 0.030.

Abstract: A display device includes a substrate including a display region; and a first pixel arranged in a first region on an outer edge of the display region, and a second pixel arranged in a second region surrounded by the first region. Each of the first pixel and the second pixel includes a first transistor, a second transistor, a first capacitor, a third transistor, and a seventh transistor. A capacitance of a capacitor connected to the gate electrode of the second transistor of the first pixel is different from a capacitance of a capacitor connected to the gate electrode of the second transistor of the second pixel.

Abstract: A semiconductor device is provided that maintains assembly and improves stress tolerance. The semiconductor device includes a plurality of trenches, a plurality of trench electrodes, an insulation film, and a first electrode. The trench electrodes are provided respectively inside the trenches. The insulation film covers two or more of the trench electrodes. The first electrode is provided on the insulation film. The insulation film has an opening provided between the two or more trench electrodes covered with the insulation film. The first electrode is provided on the semiconductor substrate to fill the opening. Each of the trench electrodes has an upper surface that includes a first recessed portion. The insulation film has an upper surface that includes a second recessed portion located immediately above the first recessed portion. The first electrode has an upper surface that includes a third recessed portion located immediately above the opening.

Abstract: A semiconductor device includes a transistor and a diode formed at a common semiconductor substrate. The diode region includes: a fifth semiconductor layer of a second conductivity type; a second semiconductor layer of the second conductivity type provided on the fifth semiconductor layer; a third semiconductor layer of a first conductivity type provided closer to a first main surface of the semiconductor substrate; a sixth semiconductor layer of the first conductivity type provided on the third semiconductor layer; and a lifetime control layer formed of a crystal defect layer reaching a deeper position than an intermediate position of the second semiconductor layer between an end of the third semiconductor layer in a thickness direction as viewed from the first main surface and an end of the fifth semiconductor layer in a thickness direction as viewed from a second main surface.

Abstract: According to one embodiment, a display device includes a pixel circuit provided in each of a plurality of pixels, a plurality of flip-flop circuits provided in a shift register and a reset element provided in each of the flip-flop circuits, and the reset element is an n-channel type transistor, the pixel circuit includes a light emitting element, a light emitting power supply and a switch element, and the light emitting element is disconnected from the light emitting power supply while the light emitting power supply is rising.

Abstract: The semiconductor device according to the present application includes: a hole injection region including a hole injection layer and a semiconductor layer of a second conductivity type; a diode region including an anode layer of a second conductivity type and a cathode layer of a first conductivity type; a boundary portion semiconductor layer of a second conductivity type provided between the diode region and the hole injection region and provided on a first main surface side; a carrier injection suppression layer of a first conductivity type provided in a surface layer of the boundary portion semiconductor layer; and a semiconductor layer of a second conductivity type provided to protrude from the hole injection region on a second main surface side.

Abstract: To effectively inhibit corrosion of a connecting terminal in an EL display, an array substrate includes a plurality of light emitting elements that are regularly arrayed, a scanning circuit that supplies the plurality of light emitting elements with at least a first scanning signal and a second scanning signal, and a plurality of connection terminals that are connected to the scanning circuit by a plurality of connection lines. The plurality of connection terminals include two adjacent connection terminals, an inverting circuit is interposed in at least one of two connection lines that connect the two adjacent connection terminals with the scanning circuit, and a same logic period in which output signals or input signals of the two adjacent connection terminals both have high potential or low potential in one scanning period is longer than a different logic period, in one scanning period.

Abstract: According to one embodiment, a display device includes a base, a first insulating layer, first and second lower electrodes, a second insulating layer including a first opening, a second opening, and a first trench, an organic layer including a light-emitting layer and an upper electrode, and the first trench includes a bottom surface and first and second side surfaces, an interval between the first side surface and the second side surface in an upper portion of the first trench is smaller than that in the bottom surface, and the organic layer includes a first portion covering the first lower electrode, a second portion covering the second lower electrode and a third portion disposed on the bottom surface.

Abstract: The semiconductor device according to the present application includes: a hole injection region including a hole injection layer and a semiconductor layer of a second conductivity type; a diode region including an anode layer of a second conductivity type and a cathode layer of a first conductivity type; a boundary portion semiconductor layer of a second conductivity type provided between the diode region and the hole injection region and provided on a first main surface side; a carrier injection suppression layer of a first conductivity type provided in a surface layer of the boundary portion semiconductor layer; and a semiconductor layer of a second conductivity type provided to protrude from the hole injection region on a second main surface side.

Abstract: An IGBT region includes: an n-type carrier accumulation layer provided to be in contact with the n?-type drift layer on the first main surface side of the n?-type drift layer and having a higher n-type impurity concentration than the n?-type drift layer, a p-type base layer provided between the n-type carrier accumulation layer and the first main surface, an n+-type emitter layer selectively provided in a surface layer portion of the p-type base layer, and a gate electrode provided to face the n+-type emitter layer and the p-type base layer with an interposition of an insulating film. A diode region includes a p-type anode layer provided between the n?-type drift layer and the first main surface and provided to a position deeper from the first main surface than a boundary between the n-type carrier accumulation layer and the n?-type drift layer.

Abstract: According to one embodiment, a display device includes a base, a first insulating layer, first and second lower electrodes, a second insulating layer including a first opening, a second opening, and a first trench, an organic layer including a light-emitting layer and an upper electrode, and the first trench includes a bottom surface and first and second side surfaces, an interval between the first side surface and the second side surface in an upper portion of the first trench is smaller than that in the bottom surface, and the organic layer includes a first portion covering the first lower electrode, a second portion covering the second lower electrode and a third portion disposed on the bottom surface.

Abstract: An IGBT region includes: an n-type carrier accumulation layer provided to be in contact with the n?-type drift layer on the first main surface side of the n?-type drift layer and having a higher n-type impurity concentration than the n?-type drift layer, a p-type base layer provided between the n-type carrier accumulation layer and the first main surface, an n+-type emitter layer selectively provided in a surface layer portion of the p-type base layer, and a gate electrode provided to face the n+-type emitter layer and the p-type base layer with an interposition of an insulating film. A diode region includes a p-type anode layer provided between the n?-type drift layer and the first main surface and provided to a position deeper from the first main surface than a boundary between the n-type carrier accumulation layer and the n?-type drift layer.