Patents by Inventor Kenji Harada

Kenji Harada has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20220310003
    Abstract: A bootstrap circuit includes a first transistor including a gate electrode, a first and a second electrodes, a capacitor connected between the gate electrode and the second electrode, and a second transistor connected to the gate electrode. In a first period, the second transistor is turned on and the gate electrode is supplied with a first analog voltage, the first transistor is turned on, and the second electrode is supplied with a precharge voltage smaller than the first analog voltage from the first electrode. In a second period, the second transistor is turned off, the first electrode is supplied with a second analog voltage, the capacitor supplies a third analog voltage to the gate electrode in response to the first analog voltage and the second analog voltage, and the second electrode is supplied with the second analog voltage from the first electrode.
    Type: Application
    Filed: March 17, 2022
    Publication date: September 29, 2022
    Applicant: Japan Display Inc.
    Inventors: Kenji HARADA, Tetsuo MORITA
  • Publication number: 20220287581
    Abstract: A monitoring device includes a receiving unit, a processing unit, and an information providing unit. The receiving unit is configured to receive a first photoplethysmogram signal acquired by irradiating a body of a subject with a first light having a first wavelength, and a heartbeat signal corresponding to a heartbeat of the subject. The processing unit is configured to calculate a fundamental frequency of heart rate corresponding to a heart rate of the subject based on the heartbeat signal, and estimate a fundamental frequency of pulse rate of the subject by comparing the fundamental frequency of heart rate with a frequency component of the first photoplethysmogram signal. The information providing unit is configured to provide information acquired based on the fundamental frequency of pulse rate.
    Type: Application
    Filed: March 1, 2022
    Publication date: September 15, 2022
    Applicant: NIHON KOHDEN CORPORATION
    Inventors: Keito KITO, Yoshiharu HARADA, Kenji MIYATA
  • Publication number: 20220271115
    Abstract: According to one embodiment, a display device including a first lower electrode, a second lower electrode, a first wiring that is disposed between the first lower electrode and the second lower electrode, a second insulation layer that is disposed on the first wiring, a first organic layer that is disposed on the first lower electrode, a second organic layer that is disposed on the second lower electrode, a first upper electrode that is disposed on the first organic layer, a second upper electrode that is disposed on the second organic layer, and a second wiring that is disposed on the second insulation layer, opposed to the first wiring, and forms a capacitance between the first wiring and the second wiring.
    Type: Application
    Filed: February 10, 2022
    Publication date: August 25, 2022
    Applicant: Japan Display Inc.
    Inventor: Kenji HARADA
  • Patent number: 11401590
    Abstract: Provided is a soft magnetic alloy having a composition of a compositional formula (Fe(1?(?+?))X1?X2?)(1?(a+b+c+d+e))PaCbSicCudMe. X1 is one or more selected from a group consisting of Co and Ni, X2 is one or more selected from a group consisting of Al, Mn, Ag, Zn, Sn, As, Sb, Bi, N, 0, and rare earth elements, and M is one or more selected from the group consisting of Nb, Hf, Zr, Ta, Ti, Mo, W and V. 0.050?a?0.17, 0<b<0.050, 0.030<c?0.10, 0<d?0.020, 0?e?0.030, ??0, ??0, and 0??+??0.50.
    Type: Grant
    Filed: May 17, 2018
    Date of Patent: August 2, 2022
    Assignee: TDK CORPORATION
    Inventors: Akihiro Harada, Hiroyuki Matsumoto, Kenji Horino, Kazuhiro Yoshidome, Akito Hasegawa, Hajime Amano, Kensuke Ara, Seigo Tokoro, Masakazu Hosono, Takuma Nakano, Satoko Mori
  • Publication number: 20220238513
    Abstract: An IGBT region includes: an n-type carrier accumulation layer provided to be in contact with the n?-type drift layer on the first main surface side of the n?-type drift layer and having a higher n-type impurity concentration than the n?-type drift layer, a p-type base layer provided between the n-type carrier accumulation layer and the first main surface, an n+-type emitter layer selectively provided in a surface layer portion of the p-type base layer, and a gate electrode provided to face the n+-type emitter layer and the p-type base layer with an interposition of an insulating film. A diode region includes a p-type anode layer provided between the n?-type drift layer and the first main surface and provided to a position deeper from the first main surface than a boundary between the n-type carrier accumulation layer and the n?-type drift layer.
    Type: Application
    Filed: November 10, 2021
    Publication date: July 28, 2022
    Applicant: Mitsubishi Electric Corporation
    Inventors: Munenori IKEDA, Tetsuya NITTA, Kenji HARADA
  • Publication number: 20220231100
    Abstract: According to one embodiment, a display device includes a base, a first insulating layer, first and second lower electrodes, a second insulating layer including a first opening, a second opening, and a first trench, an organic layer including a light-emitting layer and an upper electrode, and the first trench includes a bottom surface and first and second side surfaces, an interval between the first side surface and the second side surface in an upper portion of the first trench is smaller than that in the bottom surface, and the organic layer includes a first portion covering the first lower electrode, a second portion covering the second lower electrode and a third portion disposed on the bottom surface.
    Type: Application
    Filed: January 19, 2022
    Publication date: July 21, 2022
    Applicant: Japan Display Inc.
    Inventor: Kenji HARADA
  • Publication number: 20220195202
    Abstract: Provided is a method for surface-modifying inorganic particles having a mixing step of mixing at least a surface-modifying material and the inorganic particles to obtain a liquid mixture and a dispersion step of dispersing the inorganic particles in the liquid mixture, in which a content of the inorganic particles in the liquid mixture is 10% by mass or more and 49% by mass or less, and a total content of the surface-modifying material and the inorganic particles in the liquid mixture is 65% by mass or more and 98% by mass or less.
    Type: Application
    Filed: March 24, 2020
    Publication date: June 23, 2022
    Applicant: SUMITOMO OSAKA CEMENT CO., LTD.
    Inventors: Tomomi ITO, Kenji HARADA, Takeshi OTSUKA
  • Patent number: 11359072
    Abstract: Provided is a dispersion liquid for sealing a light-emitting element containing metal oxide particles having a refractive index of 1.7 or higher and a surface-modifying material at least partially attached to the metal oxide particles, in which a particle diameter D50 of the metal oxide particles when a cumulative percentage of a scattering intensity distribution obtained by a dynamic light scattering method is 50% is 30 nm or more and 100 nm or less, and a value D50/D90 obtained by dividing the particle diameter D50 of the metal oxide particles when the cumulative percentage of the scattering intensity distribution is 50% by a particle diameter D90 of the metal oxide particles when the cumulative percentage of the scattering intensity distribution is 90% is 0.20 or more.
    Type: Grant
    Filed: August 1, 2018
    Date of Patent: June 14, 2022
    Assignee: SUMITOMO OSAKA CEMENT CO., LTD.
    Inventors: Kenji Harada, Takeshi Otsuka
  • Publication number: 20220177709
    Abstract: A dispersion liquid according to the present invention is a dispersion liquid containing metal oxide particles which have been surface-modified with a silane compound and a silicone compound, in which, when the dispersion liquid is dried by vacuum drying to separate the metal oxide particles, and a transmission spectrum of the separated metal oxide particles is measured in a wavenumber range from 800 cm?1 to 3800 cm?1 with a Fourier transform infrared spectrophotometer, Formula (1) below: IA/IB?3.5 is satisfied (in the formula, “IA” represents a spectrum value at 3500 cm?1 and “IB” represents a spectrum value at 1100 cm?1).
    Type: Application
    Filed: March 24, 2020
    Publication date: June 9, 2022
    Applicant: SUMITOMO OSAKA CEMENT CO., LTD.
    Inventors: Tomomi ITO, Kenji HARADA, Takeshi OTSUKA
  • Publication number: 20220157899
    Abstract: According to one embodiment, a display device includes a substrate, first and second insulating layers, first and second pixel electrodes, first and second organic layers, first and second feed lines, first and second partitions, and a common electrode including first and second parts covering the first and second organic layers. The first organic layer is between the partitions. The second feed line and the second partition are located between the organic layers. The partitions are shaped such that a width of an upper part is greater than a width of a lower part. The first part is in contact with the first feed line between the first partition and the first organic layer.
    Type: Application
    Filed: October 20, 2021
    Publication date: May 19, 2022
    Applicant: Japan Display Inc.
    Inventors: Sho YANAGISAWA, Tetsuo MORITA, Kenji HARADA, Hiroshi TABATAKE, Hideyuki TAKAHASHI
  • Publication number: 20220157900
    Abstract: According to one embodiment, a display device includes a base, a first insulating layer, a first pixel electrode on the first insulating layer in a pixel, a second pixel electrode on the first insulating layer in a dummy pixel, a second insulating layer on the first insulating layer, a first organic layer in the pixel and in contact with the first pixel electrode, a second organic layer in the dummy pixel, a partition wall on the second insulating layer and between the organic layers and a common electrode covering the organic layers and the partition wall. An end portion of the first organic layer is in contact with a side surface of the partition wall.
    Type: Application
    Filed: November 16, 2021
    Publication date: May 19, 2022
    Applicant: Japan Display Inc.
    Inventors: Sho YANAGISAWA, Tetsuo MORITA, Kenji HARADA, Hiroshi TABATAKE, Hideyuki TAKAHASHI
  • Publication number: 20220109061
    Abstract: In plan view of an RC-IGBT, a boundary region has an occupancy rate of an n+-type source layer per unit area, the occupancy rate being smaller than an occupancy rate of the n+-type source layer per unit area in an IGBT region, and the boundary region has an occupancy rate of a p+-type contact layer per unit area, the occupancy rate being smaller than an occupancy rate of the p+-type contact layer per unit area in an IGBT region.
    Type: Application
    Filed: July 16, 2021
    Publication date: April 7, 2022
    Applicant: Mitsubishi Electric Corporation
    Inventors: Shinya SONEDA, Kenji HARADA, Kakeru OTSUKA
  • Patent number: 11276773
    Abstract: A semiconductor device includes: first diode trench gates extending along a first main surface from a first end side of a cell region toward a second end side thereof opposite to the first end side, the first diode trench gates being disposed adjacent to each other at a first spacing; a boundary trench gate connected to end portions of the first diode trench gates and extending in a direction intersecting a direction of extension of the first diode trench gates; and second diode trench gates having end portions connected to the boundary trench gate and extending toward the second end side of the cell region.
    Type: Grant
    Filed: November 17, 2020
    Date of Patent: March 15, 2022
    Assignee: Mitsubishi Electric Corporation
    Inventors: Shinya Soneda, Kenji Harada, Kakeru Otsuka
  • Patent number: 11264245
    Abstract: Provided is a method for manufacturing a semiconductor device that improves the reliability of the semiconductor device under thermal stress and the assembly performance of the semiconductor device in manufacturing steps. The method includes the following: forming a first electrode by depositing a first conductive film onto one main surface of a semiconductor substrate and patterning the first conductive film; forming a first metal film corresponding to a pattern of the first electrode onto the first electrode; forming a second electrode by depositing a second conductive film onto the other main surface of the semiconductor substrate; forming a second metal film thinner than the first metal film onto the second electrode; and collectively forming a third metal film onto each of the first metal film and the second metal film by electroless plating.
    Type: Grant
    Filed: October 22, 2018
    Date of Patent: March 1, 2022
    Assignee: Mitsubishi Electric Corporation
    Inventors: Shinya Soneda, Kenji Harada, Yosuke Nakata
  • Publication number: 20220037514
    Abstract: A semiconductor device includes a semiconductor substrate, a transistor region, a diode region, a boundary trench gate, and a carrier control region. The boundary trench gate is provided in a boundary portion between the transistor region and the diode region. The carrier control region is provided as a surface layer of the semiconductor substrate at a position closer to the boundary trench gate than the source layer located between the boundary trench gate and the trench gate. A concentration of first conductivity type impurities contained in the carrier control region is higher than a concentration of the first conductivity type impurities contained in the source layer or a concentration of second conductivity type impurities contained in the carrier control region is lower than a concentration of the second conductivity type impurities contained in the source layer.
    Type: Application
    Filed: May 12, 2021
    Publication date: February 3, 2022
    Applicant: Mitsubishi Electric Corporation
    Inventors: Kenji Harada, Kakeru Otsuka, Hirofumi Oki
  • Patent number: 11239329
    Abstract: According to an aspect of the present disclosure, a semiconductor device includes a semiconductor substrate, a lower electrode provided on the semiconductor substrate, an insulating film that is provided on the semiconductor substrate and surrounds the lower electrode and a metal film that is provided on the lower electrode and includes a convex portion on an upper surface thereof, wherein the convex portion includes a first portion extending in a first direction parallel to an upper surface of the semiconductor substrate, and a second portion extending in a second direction that is parallel to the upper surface of the semiconductor substrate and intersects the first direction, and the metal film is thinner than the insulating film.
    Type: Grant
    Filed: February 5, 2020
    Date of Patent: February 1, 2022
    Assignee: Mitsubishi Electric Corporation
    Inventors: Shinya Soneda, Tetsuya Nitta, Kenji Harada
  • Publication number: 20210376167
    Abstract: A semiconductor device includes a transistor and a diode formed at a common semiconductor substrate. The diode region includes: a fifth semiconductor layer of a second conductivity type; a second semiconductor layer of the second conductivity type provided on the fifth semiconductor layer; a third semiconductor layer of a first conductivity type provided closer to a first main surface of the semiconductor substrate; a sixth semiconductor layer of the first conductivity type provided on the third semiconductor layer; and a lifetime control layer formed of a crystal defect layer reaching a deeper position than an intermediate position of the second semiconductor layer between an end of the third semiconductor layer in a thickness direction as viewed from the first main surface and an end of the fifth semiconductor layer in a thickness direction as viewed from a second main surface.
    Type: Application
    Filed: February 5, 2021
    Publication date: December 2, 2021
    Applicant: Mitsubishi Electric Corporation
    Inventors: Shinya SONEDA, Kenji HARADA, Kakeru OTSUKA
  • Publication number: 20210304543
    Abstract: Entrance and exit of a person is efficiently managed by simple authentication and registration of entrance and exit using a communication terminal carried by the person.
    Type: Application
    Filed: June 10, 2021
    Publication date: September 30, 2021
    Applicant: NEC CORPORATION
    Inventors: Tomoaki NAKAO, Yukie HASEGAWA, Kenji HARADA, Kenichi URASAWA
  • Publication number: 20210305241
    Abstract: The semiconductor device according to the present application includes: a hole injection region including a hole injection layer and a semiconductor layer of a second conductivity type; a diode region including an anode layer of a second conductivity type and a cathode layer of a first conductivity type; a boundary portion semiconductor layer of a second conductivity type provided between the diode region and the hole injection region and provided on a first main surface side; a carrier injection suppression layer of a first conductivity type provided in a surface layer of the boundary portion semiconductor layer; and a semiconductor layer of a second conductivity type provided to protrude from the hole injection region on a second main surface side.
    Type: Application
    Filed: December 17, 2020
    Publication date: September 30, 2021
    Applicant: Mitsubishi Electric Corporation
    Inventors: Munenori IKEDA, Shinya SONEDA, Kenji HARADA
  • Publication number: 20210265491
    Abstract: A semiconductor device includes: first diode trench gates extending along a first main surface from a first end side of a cell region toward a second end side thereof opposite to the first end side, the first diode trench gates being disposed adjacent to each other at a first spacing; a boundary trench gate connected to end portions of the first diode trench gates and extending in a direction intersecting a direction of extension of the first diode trench gates; and second diode trench gates having end portions connected to the boundary trench gate and extending toward the second end side of the cell region.
    Type: Application
    Filed: November 17, 2020
    Publication date: August 26, 2021
    Applicant: Mitsubishi Electric Corporation
    Inventors: Shinya SONEDA, Kenji HARADA, Kakeru OTSUKA