Patents by Inventor Kenji Harada

Kenji Harada has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20210304543
    Abstract: Entrance and exit of a person is efficiently managed by simple authentication and registration of entrance and exit using a communication terminal carried by the person.
    Type: Application
    Filed: June 10, 2021
    Publication date: September 30, 2021
    Applicant: NEC CORPORATION
    Inventors: Tomoaki NAKAO, Yukie HASEGAWA, Kenji HARADA, Kenichi URASAWA
  • Publication number: 20210305241
    Abstract: The semiconductor device according to the present application includes: a hole injection region including a hole injection layer and a semiconductor layer of a second conductivity type; a diode region including an anode layer of a second conductivity type and a cathode layer of a first conductivity type; a boundary portion semiconductor layer of a second conductivity type provided between the diode region and the hole injection region and provided on a first main surface side; a carrier injection suppression layer of a first conductivity type provided in a surface layer of the boundary portion semiconductor layer; and a semiconductor layer of a second conductivity type provided to protrude from the hole injection region on a second main surface side.
    Type: Application
    Filed: December 17, 2020
    Publication date: September 30, 2021
    Applicant: Mitsubishi Electric Corporation
    Inventors: Munenori IKEDA, Shinya SONEDA, Kenji HARADA
  • Publication number: 20210265491
    Abstract: A semiconductor device includes: first diode trench gates extending along a first main surface from a first end side of a cell region toward a second end side thereof opposite to the first end side, the first diode trench gates being disposed adjacent to each other at a first spacing; a boundary trench gate connected to end portions of the first diode trench gates and extending in a direction intersecting a direction of extension of the first diode trench gates; and second diode trench gates having end portions connected to the boundary trench gate and extending toward the second end side of the cell region.
    Type: Application
    Filed: November 17, 2020
    Publication date: August 26, 2021
    Applicant: Mitsubishi Electric Corporation
    Inventors: Shinya SONEDA, Kenji HARADA, Kakeru OTSUKA
  • Patent number: 11062545
    Abstract: Entrance and exit of a person is efficiently managed by simple authentication and registration of entrance and exit using a communication terminal carried by the person.
    Type: Grant
    Filed: October 30, 2019
    Date of Patent: July 13, 2021
    Assignee: NEC CORPORATION
    Inventors: Tomoaki Nakao, Yukie Hasegawa, Kenji Harada, Kenichi Urasawa
  • Publication number: 20210175466
    Abstract: Self-luminous display panel having display region and peripheral region around the display region includes first substrate, insulating resin layer, self-luminous elements, sealing layer, attachment layer, and second substrate in this order. The insulating layer includes inner and outer sublayers with, therebetween, groove provided in the peripheral region and surrounding the display region. The sealing layer includes first-third sublayers respectively including inorganic material, resin, and inorganic material. In range including the display region and extending to at most inner end portion of the outer sublayer, the first-third sublayers are layered in this order. Outside the range, the first sublayer directly contacts the third sublayer. The attachment layer includes: peripheral layer inside peripheral portion of the second substrate; and joining layer in range surrounded by the peripheral layer.
    Type: Application
    Filed: December 4, 2020
    Publication date: June 10, 2021
    Applicant: JOLED Inc.
    Inventors: Akifumi OKIGAWA, Kenji HARADA
  • Patent number: 11031357
    Abstract: There is provided a semiconductor device having a structure that can suppress occurrence of chipping in a device region and that can reduce manufacturing cost of the semiconductor device. A semiconductor device includes a substrate and a first amorphous insulating film. The substrate has a main surface and an end surface. The main surface includes a peripheral region and a device region. The first amorphous insulating film is disposed on the peripheral region, and is separated from the device region. The first amorphous insulating film extends along the end surface in the form of a stripe. The first amorphous insulating film is flush with the end surface.
    Type: Grant
    Filed: June 8, 2020
    Date of Patent: June 8, 2021
    Assignee: Mitsubishi Electric Corporation
    Inventors: Tetsuo Takahashi, Masayoshi Tarutani, Kazuhiko Sakutani, Kenji Harada, Masao Takata, Kouichi In
  • Patent number: 10998526
    Abstract: An organic electroluminescence (EL) display panel includes a substrate; a plurality of organic EL elements; and a sealing layer in this order. In the organic EL display panel, the sealing layer has a three-layered structure in the order of a first sealing layer, a second sealing layer, and a third sealing layer. In the organic EL display panel, the first sealing layer, the second sealing layer, and the third sealing layer each include amorphous silicon nitride. In the organic EL display panel, when composition of the first sealing layer, composition of the second sealing layer, and composition of the third sealing layer are each indicated as SiNx, a value of x in the composition of the second sealing layer is greater than both a value of x in the composition of the first sealing layer and a value of x in the composition of the third sealing layer.
    Type: Grant
    Filed: September 6, 2018
    Date of Patent: May 4, 2021
    Assignee: JOLED INC.
    Inventors: Keiji Horikawa, Kenji Harada, Akifumi Okigawa
  • Patent number: 10950566
    Abstract: Provided is a technique for improving the durability of a semiconductor device. A semiconductor device includes a semiconductor substrate, an electrode on the semiconductor substrate, a solder-joining metal Him on the electrode, an oxidation-inhibiting metal film on the solder-joining metal film, and a solder layer on the oxidation-inhibiting metal film. The solder-joining metal film includes a first portion that does not overlap the oxidation-inhibiting metal film in plan view when the solder-joining metal film and the oxidation-inhibiting metal film are viewed from the oxidation-inhibiting metal film.
    Type: Grant
    Filed: June 13, 2019
    Date of Patent: March 16, 2021
    Assignee: Mitsubishi Electric Corporation
    Inventors: Kenji Harada, Shinya Soneda
  • Publication number: 20210057529
    Abstract: According to an aspect of the present disclosure, a semiconductor device includes a semiconductor substrate, a lower electrode provided on the semiconductor substrate, an insulating film that is provided on the semiconductor substrate and surrounds the lower electrode and a metal film that is provided on the lower electrode and includes a convex portion on an upper surface thereof, wherein the convex portion includes a first portion extending in a first direction parallel to an upper surface of the semiconductor substrate, and a second portion extending in a second direction that is parallel to the upper surface of the semiconductor substrate and intersects the first direction, and the metal film is thinner than the insulating film.
    Type: Application
    Filed: February 5, 2020
    Publication date: February 25, 2021
    Applicant: Mitsubishi Electric Corporation
    Inventors: Shinya SONEDA, Tetsuya NITTA, Kenji HARADA
  • Patent number: 10896863
    Abstract: A semiconductor substrate (1) has a front surface and a rear surface facing each other. A gate wiring (2) and first and second front surface electrodes (3,4) are provided on the front surface of the semiconductor substrate (1). The first and second front surface electrodes (3,4) are separated from each other by the gate wiring (2). An insulating film (7) covers the gate wiring (2). An electrode layer (8) is provided on the insulating film (7) and the first and second front surface electrodes (3,4) across the gate wiring (2). A rear surface electrode (9) is provided on the rear surface of the semiconductor substrate (1). A first plated electrode (10) is provided on the electrode layer (8). A second plated electrode (11) is provided on the rear surface electrode (9).
    Type: Grant
    Filed: January 13, 2017
    Date of Patent: January 19, 2021
    Assignee: Mitsubishi Electric Corporation
    Inventors: Yosuke Nakata, Shinya Akao, Kenji Harada
  • Patent number: 10854839
    Abstract: An organic electroluminescence (EL) display panel includes a substrate; first electrodes spaced away from each other and arrayed in rows and columns above the substrate; light-emitting layers including organic light-emitting material and disposed above the first electrodes; a second electrode disposed above the light-emitting layers; a first protection layer including resin and disposed above the second electrode but not within an auxiliary region which, in plan view, extends in a column direction between ones of the first electrodes that are adjacent in a row direction across the substrate; a second protection layer including inorganic material and disposed above the first protection layer and the second electrode; and an auxiliary electrode layer extending in the column direction within the auxiliary region and electrically connecting to the second electrode through a contact opening in the first protection layer within the auxiliary region.
    Type: Grant
    Filed: January 23, 2019
    Date of Patent: December 1, 2020
    Assignee: JOLED INC.
    Inventors: Jun Yamaguchi, Kenji Harada, Shuhei Yada
  • Publication number: 20200303323
    Abstract: There is provided a semiconductor device having a structure that can suppress occurrence of chipping in a device region and that can reduce manufacturing cost of the semiconductor device. A semiconductor device includes a substrate and a first amorphous insulating film. The substrate has a main surface and an end surface. The main surface includes a peripheral region and a device region. The first amorphous insulating film is disposed on the peripheral region, and is separated from the device region. The first amorphous insulating film extends along the end surface in the form of a stripe. The first amorphous insulating film is flush with the end surface.
    Type: Application
    Filed: June 8, 2020
    Publication date: September 24, 2020
    Applicant: Mitsubishi Electric Corporation
    Inventors: Tetsuo TAKAHASHI, Masayoshi TARUTANI, Kazuhiko SAKUTANI, Kenji HARADA, Masao TAKATA, Kouichi IN
  • Patent number: 10770683
    Abstract: An organic electroluminescence (EL) display panel including: a substrate; an insulating resin layer extending from an image display region to a peripheral region; an organic EL element array within the image display region; a sealing layer extending from the image display region to the peripheral region; and a sealing reinforcement layer, laminated in this order. The sealing layer includes first, second, and third sealing layers laminated in this order from the substrate, the first and third sealing layers being made of an inorganic material and the second sealing layer being made of a resin. In the outer peripheral portion of the sealing layer, the first and third sealing layers are in direct contact with each other and cover an outer end of the insulating resin layer. An outer end of the sealing reinforcement layer is outside the outer end of the insulating resin layer in plan view.
    Type: Grant
    Filed: December 20, 2018
    Date of Patent: September 8, 2020
    Assignee: JOLED INC.
    Inventor: Kenji Harada
  • Patent number: 10756029
    Abstract: There is provided a semiconductor device having a structure that can suppress occurrence of chipping in a device region and that can reduce manufacturing cost of the semiconductor device. A semiconductor device includes a substrate and a first amorphous insulating film. The substrate has a main surface and an end surface. The main surface includes a peripheral region and a device region. The first amorphous insulating film is disposed on the peripheral region, and is separated from the device region. The first amorphous insulating film extends along the end surface in the form of a stripe. The first amorphous insulating film is flush with the end surface.
    Type: Grant
    Filed: December 11, 2017
    Date of Patent: August 25, 2020
    Assignee: Mitsubishi Electric Corporation
    Inventors: Tetsuo Takahashi, Masayoshi Tarutani, Kazuhiko Sakutani, Kenji Harada, Masao Takata, Kouichi In
  • Patent number: 10720395
    Abstract: There is provided a semiconductor device having a structure that can suppress occurrence of chipping in a device region and that can reduce manufacturing cost of the semiconductor device. A semiconductor device includes a substrate and a first amorphous insulating film. The substrate has a main surface and an end surface. The main surface includes a peripheral region and a device region. The first amorphous insulating film is disposed on the peripheral region, and is separated from the device region. The first amorphous insulating film extends along the end surface in the form of a stripe. The first amorphous insulating film is flush with the end surface.
    Type: Grant
    Filed: December 11, 2017
    Date of Patent: July 21, 2020
    Assignee: Mitsubishi Electric Corporation
    Inventors: Tetsuo Takahashi, Masayoshi Tarutani, Kazuhiko Sakutani, Kenji Harada, Masao Takata, Kouichi In
  • Publication number: 20200143612
    Abstract: Entrance and exit of a person is efficiently managed by simple authentication and registration of entrance and exit using a communication terminal carried by the person.
    Type: Application
    Filed: October 30, 2019
    Publication date: May 7, 2020
    Applicant: NEC CORPORATION
    Inventors: Tomoaki NAKAO, Yukie HASEGAWA, Kenji HARADA, Kenichi URASAWA
  • Publication number: 20200115529
    Abstract: Provided is a dispersion liquid for sealing a light-emitting element containing metal oxide particles having a refractive index of 1.7 or higher and a surface-modifying material at least partially attached to the metal oxide particles, in which a particle diameter D50 of the metal oxide particles when a cumulative percentage of a scattering intensity distribution obtained by a dynamic light scattering method is 50% is 30 nm or more and 100 nm or less, and a content of the surface-modifying material not attached to the metal oxide particles is 60% by mass or less with respect to a total content of the metal oxide particles and the surface-modifying material.
    Type: Application
    Filed: August 1, 2018
    Publication date: April 16, 2020
    Applicant: SUMITOMO OSAKA CEMENT CO., LTD.
    Inventors: KENJI HARADA, TAKESHI OTSUKA
  • Publication number: 20200115530
    Abstract: Provided is a dispersion liquid for sealing a light-emitting element containing metal oxide particles having a refractive index of 1.7 or higher and a surface-modifying material at least partially attached to the metal oxide particles, in which a particle diameter D50 of the metal oxide particles when a cumulative percentage of a scattering intensity distribution obtained by a dynamic light scattering method is 50% is 30 nm or more and 100 nm or less, and a value D50/D90 obtained by dividing the particle diameter D50 of the metal oxide particles when the cumulative percentage of the scattering intensity distribution is 50% by a particle diameter D90 of the metal oxide particles when the cumulative percentage of the scattering intensity distribution is 90% is 0.20 or more.
    Type: Application
    Filed: August 1, 2018
    Publication date: April 16, 2020
    Applicant: SUMITOMO OSAKA CEMENT CO., LTD.
    Inventors: Kenji HARADA, Takeshi OTSUKA
  • Publication number: 20200013741
    Abstract: Provided is a technique for improving the durability of a semiconductor device. A semiconductor device includes a semiconductor substrate, an electrode on the semiconductor substrate, a solder-joining metal Him on the electrode, an oxidation-inhibiting metal film on the solder-joining metal film, and a solder layer on the oxidation-inhibiting metal film. The solder-joining metal film includes a first portion that does not overlap the oxidation-inhibiting metal film in plan view when the solder-joining metal film and the oxidation-inhibiting metal film are viewed from the oxidation-inhibiting metal film.
    Type: Application
    Filed: June 13, 2019
    Publication date: January 9, 2020
    Applicant: Mitsubishi Electric Corporation
    Inventors: Kenji HARADA, Shinya SONEDA
  • Publication number: 20190363279
    Abstract: An organic electroluminescence (EL) display panel includes a substrate; first electrodes spaced away from each other and arrayed in rows and columns above the substrate; light-emitting layers including organic light-emitting material and disposed above the first electrodes; a second electrode disposed above the light-emitting layers; a first protection layer including resin and disposed above the second electrode but not within an auxiliary region which, in plan view, extends in a column direction between ones of the first electrodes that are adjacent in a row direction across the substrate; a second protection layer including inorganic material and disposed above the first protection layer and the second electrode; and an auxiliary electrode layer extending in the column direction within the auxiliary region and electrically connecting to the second electrode through a contact opening in the first protection layer within the auxiliary region.
    Type: Application
    Filed: January 23, 2019
    Publication date: November 28, 2019
    Inventors: Jun YAMAGUCHI, Kenji HARADA, Shuhei YADA