Patents by Inventor Kenji Harafuji

Kenji Harafuji has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 8686544
    Abstract: It is possible to realize the following package structure. That is, a structure for applying a stress to a channel region is provided for a semiconductor chip itself. In a package manufacturing process, a low thermal expansion coefficient film is formed on a circuit face of an Si chip. Thus, distribution and magnitude of a desired stress can be secured for a channel region of a MOSFET in a mounted chip even after performance of the package manufacturing process. As a result, a mobility is increased and current driving power is enhanced.
    Type: Grant
    Filed: November 13, 2006
    Date of Patent: April 1, 2014
    Assignee: Panasonic Corporation
    Inventors: Kenji Harafuji, Kimihito Kuwabara
  • Publication number: 20070108532
    Abstract: It is possible to realize the following package structure. That is, a structure for applying a stress to a channel region is provided for a semiconductor chip itself. In a package manufacturing process, a low thermal expansion coefficient film is formed on a circuit face of an Si chip. Thus, distribution and magnitude of a desired stress can be secured for a channel region of a MOSFET in a mounted chip even after performance of the package manufacturing process. As a result, a mobility is increased and current driving power is enhanced.
    Type: Application
    Filed: November 13, 2006
    Publication date: May 17, 2007
    Applicant: Matsushita Electric Industrial Co., Ltd.
    Inventors: Kenji Harafuji, Kimihito Kuwabara
  • Patent number: 7160748
    Abstract: The method for fabricating a nitride semiconductor of the present invention includes the steps of: (1) growing a first semiconductor layer made of a first group III nitride over a substrate by supplying a first group III source and a group V source containing nitrogen; and (2) growing a second semiconductor layer made of a second group III nitride on the first semiconductor layer by supplying a second group III source and a group V source containing nitrogen. At least one of the steps (1) and (2) includes the step of supplying a p-type dopant over the substrate, and an area near the interface between the first semiconductor layer and the second semiconductor layer is grown so that the density of the p-type dopant locally increases.
    Type: Grant
    Filed: February 24, 2005
    Date of Patent: January 9, 2007
    Assignee: Matsushita Electric Industrial Co., Ltd.
    Inventors: Akihiko Ishibashi, Ayumu Tsujimura, Yoshiaki Hasegawa, Nobuyuki Otsuka, Gaku Sugahara, Ryoko Miyanaga, Toshitaka Shimamoto, Kenji Harafuji, Yuzaburo Ban, Kiyoshi Ohnaka
  • Patent number: 6921678
    Abstract: The method for fabricating a nitride semiconductor of the present invention includes the steps of: (1) growing a first semiconductor layer made of a first group III nitride over a substrate by supplying a first group III source and a group V source containing nitrogen; and (2) growing a second semiconductor layer made of a second group III nitride on the first semiconductor layer by supplying a second group III source and a group V source containing nitrogen. At least one of the steps (1) and (2) includes the step of supplying a p-type dopant over the substrate, and an area near the interface between the first semiconductor layer and the second semiconductor layer is grown so that the density of the p-type dopant locally increases.
    Type: Grant
    Filed: May 9, 2003
    Date of Patent: July 26, 2005
    Assignee: Matsushita Electric Industrial Co., Ltd.
    Inventors: Akihiko Ishibashi, Ayumu Tsujimura, Yoshiaki Hasegawa, Nobuyuki Otsuka, Gaku Sugahara, Ryoko Miyanaga, Toshitaka Shimamoto, Kenji Harafuji, Yuzaburo Ban, Kiyoshi Ohnaka
  • Publication number: 20050142682
    Abstract: The method for fabricating a nitride semiconductor of the present invention includes the steps of: (1) growing a first semiconductor layer made of a first group III nitride over a substrate by supplying a first group III source and a group V source containing nitrogen; and (2) growing a second semiconductor layer made of a second group III nitride on the first semiconductor layer by supplying a second group III source and a group V source containing nitrogen. At least one of the steps (1) and (2) includes the step of supplying a p-type dopant over the substrate, and an area near the interface between the first semiconductor layer and the second semiconductor layer is grown so that the density of the p-type dopant locally increases.
    Type: Application
    Filed: February 24, 2005
    Publication date: June 30, 2005
    Applicant: Matsushita Electric Industrial Co., Ltd.
    Inventors: Akihiko Ishibashi, Ayumu Tsujimura, Yoshiaki Hasegawa, Nobuyuki Otsuka, Gaku Sugahara, Ryoko Miyanaga, Toshitaka Shimamoto, Kenji Harafuji, Yuzaburo Ban, Kiyoshi Ohnaka
  • Patent number: 6867112
    Abstract: The method of fabricating a nitride semiconductor device of this invention includes plural steps of respectively growing plural nitride semiconductor layers on a substrate; and between a step of growing one nitride semiconductor layer and a step of growing another nitride semiconductor layer adjacent to the one nitride semiconductor layer among the plural steps, a step of changing a growth ambient pressure from a first growth ambient pressure to a second growth ambient pressure different from the first growth ambient pressure.
    Type: Grant
    Filed: October 20, 2000
    Date of Patent: March 15, 2005
    Assignee: Matsushita Electric Industrial Co., Ltd.
    Inventors: Akihiko Ishibashi, Isao Kidoguchi, Kenji Harafuji, Yuzaburo Ban
  • Patent number: 6737684
    Abstract: There is provided a MQB layer as a multi-quantum barrier portion composed of well layers and barrier layers that are formed of extremely thin films having different compositions and alternately stacked. This enhances an effective barrier height by using the phenomenon that holes likely to flow from a SiGe base layer to a Si emitter layer are reflected by the MQB layer and thereby suppresses the reverse injection of the holes from the SiGe base layer into the Si emitter layer. As a result, the reverse injection of carriers is suppressed by the MQB layer even when the base doping concentration is increased, which provides a satisfactory current amplification factor and increases a maximum oscillation frequency. What results is a bipolar transistor having excellent RF characteristics such as current amplification factor, current gain cutoff frequency, and maximum oscillation frequency in a microwave band or the like.
    Type: Grant
    Filed: September 11, 2000
    Date of Patent: May 18, 2004
    Assignee: Matsushita Electric Industrial Co., Ltd.
    Inventors: Takeshi Takagi, Kenji Harafuji
  • Patent number: 6667185
    Abstract: The method of fabricating a nitride semiconductor device of this invention includes plural steps of respectively growing plural nitride semiconductor layers on a substrate; and between a step of growing one nitride semiconductor layer and a step of growing another nitride semiconductor layer adjacent to the one nitride semiconductor layer among the plural steps, a step of changing a growth ambient pressure from a first growth ambient pressure to a second growth ambient pressure different from the first growth ambient pressure.
    Type: Grant
    Filed: January 31, 2003
    Date of Patent: December 23, 2003
    Assignee: Matsushita Electric Industrial Co., Ltd.
    Inventors: Akihiko Ishibashi, Isao Kidoguchi, Kenji Harafuji, Yuzaburo Ban
  • Publication number: 20030203629
    Abstract: The method for fabricating a nitride semiconductor of the present invention includes the steps of: (1) growing a first semiconductor layer made of a first group III nitride over a substrate by supplying a-first group III source and a group V source containing nitrogen; and (2) growing a second semiconductor layer made of a second group III nitride on the first semiconductor layer by supplying a second group III source and a group V source containing nitrogen. At least one of the steps (1) and (2) includes the step of supplying a p-type dopant over the substrate, and an area near the interface between the first semiconductor layer and the second semiconductor layer is grown so that the density of the p-type dopant locally increases.
    Type: Application
    Filed: May 9, 2003
    Publication date: October 30, 2003
    Applicant: Matsushita Electric Industrial Co., Ltd.
    Inventors: Akihiko Ishibashi, Ayumu Tsujimura, Yoshiaki Hasegawa, Nobuyuki Otsuka, Gaku Sugahara, Ryoko Miyanaga, Toshitaka Shimamoto, Kenji Harafuji, Yuzaburo Ban, Kiyoshi Ohnaka
  • Publication number: 20030143765
    Abstract: The method of fabricating a nitride semiconductor device of this invention includes plural steps of respectively growing plural nitride semiconductor layers on a substrate; and between a step of growing one nitride semiconductor layer and a step of growing another nitride semiconductor layer adjacent to the one nitride semiconductor layer among the plural steps, a step of changing a growth ambient pressure from a first growth ambient pressure to a second growth ambient pressure different from the first growth ambient pressure.
    Type: Application
    Filed: January 31, 2003
    Publication date: July 31, 2003
    Applicant: Matsushita Electric Industrial Co., Ltd.
    Inventors: Akihiko Ishibashi, Isao Kidoguchi, Kenji Harafuji, Yuzaburo Ban
  • Patent number: 6586774
    Abstract: The method for fabricating a nitride semiconductor of the present invention includes the steps of: (1) growing a first semiconductor layer made of a first group III nitride over a substrate by supplying a first group III source and a group V source containing nitrogen; and (2) growing a second semiconductor layer made of a second group III nitride on the first semiconductor layer by supplying a second group III source and a group V source containing nitrogen. At least one of the steps (1) and (2) includes the step of supplying a p-type dopant over the substrate, and an area near the interface between the first semiconductor layer and the second semiconductor layer is grown so that the density of the p-type dopant locally increases.
    Type: Grant
    Filed: December 19, 2001
    Date of Patent: July 1, 2003
    Assignee: Matsushita Electric Industrial Co., Ltd.
    Inventors: Akihiko Ishibashi, Ayumu Tsujimura, Yoshiaki Hasegawa, Nobuyuki Otsuka, Gaku Sugahara, Ryoko Miyanaga, Toshitaka Shimamoto, Kenji Harafuji, Yuzaburo Ban, Kiyoshi Ohnaka
  • Patent number: 6544869
    Abstract: A method for depositing a semiconductor film on a wafer by making a source gas supplied flow almost horizontally to the surface of the wafer. When a process condition, e.g., the flow velocity or pressure of the source gas, should be changed, the source gas has its velocity and/or pressure changed so that the source gas is supplied at a substantially constant flow rate.
    Type: Grant
    Filed: June 20, 2001
    Date of Patent: April 8, 2003
    Assignee: Matsushita Electric Industrial Co., Ltd.
    Inventors: Kenji Harafuji, Akihiko Ishibashi, Yuzaburo Ban, Kiyoshi Ohnaka
  • Publication number: 20020195054
    Abstract: A method for depositing a semiconductor film on a wafer by making a source gas supplied flow almost horizontally to the surface of the wafer. When a process condition, e.g., the flow velocity or pressure of the source gas, should be changed, the source gas has its velocity and/or pressure changed so that the source gas is supplied at a substantially constant flow rate.
    Type: Application
    Filed: July 15, 2002
    Publication date: December 26, 2002
    Applicant: MATSUSHITA ELECTRIC INDUSTRIAL CO., LTD.
    Inventors: Kenji Harafuji, Akihiko Ishibashi, Yuzaburo Ban, Kiyoshi Ohnaka
  • Patent number: 6466597
    Abstract: A nitride semiconductor laser device includes an n-type contact layer of n-type GaN and an n-type cladding layer of n-type Al0.35Ga0.65N formed on a substrate of sapphire. On the n-type cladding layer, a multiple quantum well active layer of Al0.2Ga0.8N/Al0.25Ga0.75N, a p-type leak barrier layer of p-type Al0.5Ga0.5N0.975P0.025 and a p-type cladding layer of p-type Al0.4Ga0.6N0.98P0.02 are successively formed. The p-type leak barrier layer has a wider energy gap than the n-type cladding layer, and the p-type leak barrier layer and the p-type cladding layer include phosphorus for making an acceptor level shallow with keeping a wide energy gap.
    Type: Grant
    Filed: June 14, 1999
    Date of Patent: October 15, 2002
    Assignee: Matsushita Electric Industrial Co., Ltd.
    Inventors: Masahiro Kume, Yuzaburo Ban, Kenji Harafuji, Isao Kidoguchi, Satoshi Kamiyama, Ayumu Tsujimura, Ryoko Miyanaga, Akihiko Ishibashi, Yoshiaki Hasegawa
  • Publication number: 20020081763
    Abstract: The method for fabricating a nitride semiconductor of the present invention includes the steps of: (1) growing a first semiconductor layer made of a first group III nitride over a substrate by supplying a first group III source and a group V source containing nitrogen; and (2) growing a second semiconductor layer made of a second group III nitride on the first semiconductor layer by supplying a second group III source and a group V source containing nitrogen. At least one of the steps (1) and (2) includes the step of supplying a p-type dopant over the substrate, and an area near the interface between the first semiconductor layer and the second semiconductor layer is grown so that the density of the p-type dopant locally increases.
    Type: Application
    Filed: December 19, 2001
    Publication date: June 27, 2002
    Inventors: Akihiko Ishibashi, Ayumu Tsujimura, Yoshiaki Hasegawa, Nobuyuki Otsuka, Gaku Sugahara, Ryoko Miyanaga, Toshitaka Shimamoto, Kenji Harafuji, Yuzaburo Ban, Kiyoshi Ohnaka
  • Publication number: 20010032588
    Abstract: A semiconductor film deposition apparatus includes: a susceptor for holding a substrate thereon; a reactor body covering the susceptor so that the substrate is exposed inside the reactor body; and a gas inlet portion. The gas inlet portion has an opening with a width smaller than that of the susceptor. Through the gas inlet portion, a source gas is introduced onto the substrate substantially horizontally to the surface of the substrate. And the gas inlet portion is connected airtightly to the reactor body. An inner wall of the gas inlet portion includes a finely roughened region.
    Type: Application
    Filed: April 20, 2001
    Publication date: October 25, 2001
    Inventors: Kenji Harafuji, Yuzaburo Ban
  • Patent number: 5928528
    Abstract: A reactive gas supplied to a chamber 1 is put into plasma by supplying radio frequency power to the chamber 1 intermittently or while repeating high and low levels alternately and a specimen A in the chamber 1 is treated by the plasma. A positive pulse-like bias voltage synchronized with a period in which the radio frequency power is not supplied or a period in which low-level power is supplied is applied to the specimen A for preventing charging.
    Type: Grant
    Filed: September 2, 1997
    Date of Patent: July 27, 1999
    Assignee: Matsushita Electric Industrial Co., Ltd.
    Inventors: Masafumi Kubota, Shigenori Hayashi, Michinari Yamanaka, Kenji Harafuji
  • Patent number: 5869402
    Abstract: A reactive gas is introduced into a vacuum chamber by a gas controller so that a plasma is generated in a plasma generation region. Subsequently, high-frequency power from a high-frequency power source is applied to a sample stage in the vacuum chamber so that ions in the plasma are made incident upon the sample stage, thereby performing dry etching with respect to a sample on the sample stage. In main etching, a value of (pressure of reactive gas)/(frequency of high-frequency power) is reduced so as to reduce a scattering probability, which is the probability of ions being scattered in collision with neutral particles in a sheath region, thereby increasing the energy of ion fluxes and making the incidence directions of the ion fluxes perpendicular to a surface of the sample stage.
    Type: Grant
    Filed: May 10, 1995
    Date of Patent: February 9, 1999
    Assignee: Matsushita Electric Industrial Co., Ltd.
    Inventors: Kenji Harafuji, Masafumi Kubota
  • Patent number: 5635021
    Abstract: There is disclosed a dry etching method capable of achieving the formation of vertical line patterns and the minimization of a difference in size between an isolated line pattern and an inner line pattern. When the line width of an inner line pattern is smaller than that of an isolated line pattern and when the width of a line pattern is greater than the width of a resist pattern, at least one parameter selected from the parameter group consisting of the pressure of a raw-material gas mixture introduced into a vacuum chamber, the exhaust amount of gas discharged from the vacuum chamber, a high-frequency electric power, the frequency of the high-frequency electric power, the rate of a lateral wall protecting gas in the raw-material gas mixture and the temperature of a sample stand, is changed such that the amounts in which the line patterns are etched, are increased and that the amount in which the inner line pattern is etched, is smaller than the amount in which the isolated line pattern is etched.
    Type: Grant
    Filed: November 17, 1995
    Date of Patent: June 3, 1997
    Assignee: Matsushita Electric Industrial Co., Ltd.
    Inventor: Kenji Harafuji
  • Patent number: 5424905
    Abstract: Three electrodes are disposed at lateral sides of a plasma generating chamber of an etching apparatus serving as a plasma generating apparatus. A sample stage is disposed at a lower part of the plasma generating chamber, and an opposite electrode is disposed at an upper part thereof. High frequency electric power having a first frequency is supplied to the sample stage and the opposite electrode. Respectively supplied to the three electrodes 4, 5, 6 are high frequency electric powers which are oscillated by a three-phase magnetron, which have a second frequency different from the first frequency and of which respective phases are successively different by about 120.degree. from one another, thus forming a rotational electric field in the plasma generating chamber.
    Type: Grant
    Filed: March 30, 1993
    Date of Patent: June 13, 1995
    Assignee: Matsushita Electric Company, Ltd.
    Inventors: Noboru Nomura, Kenji Harafuji, Masafumi Kubota, Tokuhiko Tamaki, Mitsuhiro Ohkuni, Ichiro Nakayama