Patents by Inventor Kenji Hinode
Kenji Hinode has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 8129275Abstract: In order to provide an anticorrosive technique for metal wirings formed by a chemical mechanical polishing (CMP) method, a process for manufacturing a semiconductor integrated circuit device according to the invention comprises the steps of: forming a metal layer of Cu (or a Cu alloy containing Cu as a main component) over the major face of a wafer and then planarizing the metal layer by a chemical mechanical polishing (CMP) method to form metal wirings; anticorroding the planarized major face of the wafer to form a hydrophobic protective film over the surfaces of the metal wirings; immersing the anticorroded major face of the wafer or keeping the same in a wet state so that it may not become dry; and post-cleaning the major face, kept in the wet state, of the wafer.Type: GrantFiled: February 5, 2010Date of Patent: March 6, 2012Assignee: Renesas Electronics CorporationInventors: Naofumi Ohashi, Junji Noguchi, Toshinori Imai, Hizuru Yamaguchi, Nobuo Owada, Kenji Hinode, Yoshio Homma, Seiichi Kondo
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Patent number: 7947596Abstract: A semiconductor device according to this invention comprises a substrate 100 in which semiconductor elements are formed, a first conductor 301 at least a portion of the peripheral surface of which is made of a material comprising copper as a main ingredient, and a first insulative diffusion barrier layer 203 covering at least a portion of the first conductor 301. The first insulative diffusion barrier layer 203 is formed by using a gas mixture at least containing an alkoxy silane represented by the general formula (RO)nSiH4?n (n is an integer in a range from 1 to 3, R represents an alkyl group, an aryl group or a derivative thereof), and an oxidative gas by a plasma CVD. Thus, a semiconductor device comprising copper wiring of high reliability and with less wiring delay time can be provided.Type: GrantFiled: September 26, 2006Date of Patent: May 24, 2011Assignee: Renesas Electronics CorporationInventors: Kenichi Takeda, Daisuke Ryuzaki, Kenji Hinode, Toshiyuki Mine
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Publication number: 20100136786Abstract: In order to provide an anticorrosive technique for metal wirings formed by a chemical mechanical polishing (CMP) method, a process for manufacturing a semiconductor integrated circuit device according to the invention comprises the steps of: forming a metal layer of Cu (or a Cu alloy containing Cu as a main component) over the major face of a wafer and then planarizing the metal layer by a chemical mechanical polishing (CMP) method to form metal wirings; anticorroding the planarized major face of the wafer to form a hydrophobic protective film over the surfaces of the metal wirings; immersing the anticorroded major face of the wafer or keeping the same in a wet state so that it may not become dry; and post-cleaning the major face, kept in the wet state, of the wafer.Type: ApplicationFiled: February 5, 2010Publication date: June 3, 2010Inventors: Naofumi Ohashi, Junji Noguchi, Toshinori Imai, Hizuru Yamaguchi, Nobuo Owada, Kenji Hinode, Yoshio Homma, Seiichi Kondo
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Patent number: 7659201Abstract: In order to provide an anticorrosive technique for metal wirings formed by a chemical mechanical polishing (CMP) method, a process for manufacturing a semiconductor integrated circuit device according to the invention comprises the steps of: forming a metal layer of Cu (or a Cu alloy containing Cu as a main component) over the major face of a wafer and then planarizing the metal layer by a chemical mechanical polishing (CMP) method to form metal wirings; anticorroding the planarized major face of the wafer to form a hydrophobic protective film over the surfaces of the metal wirings; immersing the anticorroded major face of the wafer or keeping the same in a wet state so that it may not become dry; and post-cleaning the major face, kept in the wet state, of the wafer.Type: GrantFiled: May 27, 2008Date of Patent: February 9, 2010Assignee: Renesas Technology Corp.Inventors: Naofumi Ohashi, Junji Noguchi, Toshinori Imai, Hizuru Yamaguchi, Nobuo Owada, Kenji Hinode, Yoshio Homma, Seiichi Kondo
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Patent number: 7563716Abstract: A polishing technique wherein scratches, peeling, dishing and erosion are suppressed, a complex cleaning process and slurry supply/processing equipment are not required, and the cost of consumable items such as slurries and polishing pads is reduced. A metal film formed on an insulating film comprising a groove is polished with a polishing solution containing an oxidizer and a substance which renders oxides water-soluble, but not containing a polishing abrasive.Type: GrantFiled: March 29, 2007Date of Patent: July 21, 2009Assignee: Renesas Technology Corp.Inventors: Seiichi Kondo, Yoshio Homma, Noriyuki Sakuma, Kenichi Takeda, Kenji Hinode
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Patent number: 7510970Abstract: In order to provide an anticorrosive technique for metal wirings formed by a chemical mechanical polishing (CMP) method, a process for manufacturing a semiconductor integrated circuit device according to the invention comprises the steps of: forming a metal layer of Cu (or a Cu alloy containing Cu as a main component) over the major face of a wafer and then planarizing the metal layer by a chemical mechanical polishing (CMP) method to form metal wirings; anticorroding the planarized major face of the wafer to form a hydrophobic protective film over the surfaces of the metal wirings; immersing the anticorroded major face of the wafer or keeping the same in a wet state so that it may not become dry; and post-cleaning the major face, kept in the wet state, of the wafer.Type: GrantFiled: February 21, 2006Date of Patent: March 31, 2009Assignee: Renesas Technology Corp.Inventors: Naofumi Ohashi, Junji Noguchi, Toshinori Imai, Hizuru Yamaguchi, Nobuo Owada, Kenji Hinode, Yoshio Homma, Seiichi Kondo
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Publication number: 20080233736Abstract: In order to provide an anticorrosive technique for metal wirings formed by a chemical mechanical polishing (CMP) method, a process for manufacturing a semiconductor integrated circuit device according to the invention comprises the steps of: forming a metal layer of Cu (or a Cu alloy containing Cu as a main component) over the major face of a wafer and then planarizing the metal layer by a chemical mechanical polishing (CMP) method to form metal wirings; anticorroding the planarized major face of the wafer to form a hydrophobic protective film over the surfaces of the metal wirings; immersing the anticorroded major face of the wafer or keeping the same in a wet state so that it may not become dry; and post-cleaning the major face, kept in the wet state, of the wafer.Type: ApplicationFiled: May 27, 2008Publication date: September 25, 2008Inventors: Naofumi Ohashi, Junji Noguchi, Toshinori Imai, Hizuru Yamaguchi, Nobuo Owada, Kenji Hinode, Yoshio Homma, Seiichi Kondo
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Patent number: 7279425Abstract: A polishing technique wherein scratches, peeling, dishing and erosion are suppressed, a complex cleaning process and slurry supply/processing equipment are not required, and the cost of consumable items such as slurries and polishing pads is reduced. A metal film formed on an insulating film comprising a groove is polished with a polishing solution containing an oxidizer and a substance which renders oxides water-soluble, but not containing a polishing abrasive.Type: GrantFiled: October 17, 2006Date of Patent: October 9, 2007Assignee: Hitachi, Ltd.Inventors: Seiichi Kondo, Yoshio Homma, Noriyuki Sakuma, Kenichi Takeda, Kenji Hinode
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Publication number: 20070167015Abstract: A polishing technique wherein scratches, peeling, dishing and erosion are suppressed, a complex cleaning process and slurry supply/processing equipment are not required, and the cost of consumable items such as slurries and polishing pads is reduced. A metal film formed on an insulating film comprising a groove is polished with a polishing solution containing an oxidizer and a substance which renders oxides water-soluble, but not containing a polishing abrasive.Type: ApplicationFiled: March 29, 2007Publication date: July 19, 2007Inventors: Seiichi Kondo, Yoshio Homma, Noriyuki Sakuma, Kenichi Takeda, Kenji Hinode
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Publication number: 20070029285Abstract: A polishing technique wherein scratches, peeling, dishing and erosion are suppressed, a complex cleaning process and slurry supply/processing equipment are not required, and the cost of consumable items such as slurries and polishing pads is reduced. A metal film formed on an insulating film comprising a groove is polished with a polishing solution containing an oxidizer and a substance which renders oxides water-soluble, but not containing a polishing abrasive.Type: ApplicationFiled: October 17, 2006Publication date: February 8, 2007Inventors: Seiichi Kondo, Yoshio Homma, Noriyuki Sakuma, Kenichi Takeda, Kenji Hinode
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Publication number: 20070018330Abstract: A semiconductor device according to this invention comprises a substrate 100 in which semiconductor elements are formed, a first conductor 301 at least a portion of the peripheral surface of which is made of a material comprising copper as a main ingredient, and a first insulative diffusion barrier layer 203 covering at least a portion of the first conductor 301. The first insulative diffusion barrier layer 203 is formed by using a gas mixture at least containing an alkoxy silane represented by the general formula (RO)nSiH4?n (n is an integer in a range from 1 to 3, R represents an alkyl group, an aryl group or a derivative thereof), and an oxidative gas by a plasma CVD. Thus, a semiconductor device comprising copper wiring of high reliability and with less wiring delay time can be provided.Type: ApplicationFiled: September 26, 2006Publication date: January 25, 2007Inventors: Kenichi Takeda, Daisuke Ryuzaki, Kenji Hinode, Toshiyuki Mine
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Patent number: 7132367Abstract: A polishing technique wherein scratches, peeling, dishing and erosion are suppressed, a complex cleaning process and slurry supply/processing equipment are not required, and the cost of consumable items such as slurries and polishing pads is reduced A metal film formed on an insulating film comprising a groove is polished with a polishing solution containing an oxidizer and a substance which renders oxides water-soluble, but not containing a polishing abrasive.Type: GrantFiled: May 20, 2003Date of Patent: November 7, 2006Assignee: Hitachi, Ltd.Inventors: Seiichi Kondo, Yoshio Homma, Noriyuki Sakuma, Kenichi Takeda, Kenji Hinode
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Patent number: 7122900Abstract: A semiconductor device according to this invention comprises a substrate 100 in which semiconductor elements are formed, a first conductor 301 at least a portion of the peripheral surface of which is made of a material comprising copper as a main ingredient, and a first insulative diffusion barrier layer 203 covering at least a portion of the first conductor 301. The first insulative diffusion barrier layer 203 is formed by using a gas mixture at least containing an alkoxy silane represented by the general formula (RO)nSiH4?n (n is an integer in a range from 1 to 3, R represents an alkyl group, an aryl group or a derivative thereof), and an oxidative gas by a plasma CVD. Thus, a semiconductor device comprising copper wiring of high reliability and with less wiring delay time can be provided.Type: GrantFiled: May 28, 2001Date of Patent: October 17, 2006Assignee: Renesas Technology Corp.Inventors: Kenichi Takeda, Daisuke Ryuzaki, Kenji Hinode, Toshiyuki Mine
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Patent number: 7081417Abstract: To provide a planarization method which does not depend upon the size and the density of a wiring pattern and in which a reliable wiring system and a Josephson device can be formed and wiring structure, an insulation layer is planarized by forming a reversal pattern mask of wiring and selectively removing the insulation layer on the wiring.Type: GrantFiled: June 24, 2004Date of Patent: July 25, 2006Assignees: Hitachi, Ltd., NEC Corporation, International Superconductivity Technology Center, the Judicial FoundationInventors: Kenji Hinode, Shuichi Nagasawa, Yoshihiro Kitagawa, Mutsuo Hidaka, Keiichi Tanabe
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Publication number: 20060141792Abstract: In order to provide an anticorrosive technique for metal wirings formed by a chemical mechanical polishing (CMP). method, a process for manufacturing. a semiconductor integrated circuit device according to the invention comprises the steps of: forming a metal layer of Cu (or a Cu alloy containing Cu as a main component) over the major face of a wafer and then planarizing the metal layer by a chemical mechanical polishing (CMP) method to form metal wirings; anticorroding the planarized major face of the wafer to form a hydrophobic protective film over the surfaces of the metal wirings; immersing the anticorroded major face of the wafer or keeping the same in a wet state so that it may not become dry; and post-cleaning the major face, kept in the wet state, of the wafer.Type: ApplicationFiled: February 21, 2006Publication date: June 29, 2006Inventors: Naofumi Ohashi, Junji Noguchi, Toshinori Imai, Hizuru Yamaguchi, Nobuo Owada, Kenji Hinode, Yoshio Homma, Seiichi Kondo
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Publication number: 20050074967Abstract: A polishing technique wherein scratches, peeling, dishing and erosion are suppressed, a complex cleaning process and slurry supply/processing equipment are not required, and the cost of consumable items such as slurries and polishing pads is reduced A metal film formed on an insulating film comprising a groove is polished with a polishing solution containing an oxidizer and a substance which renders oxides water-soluble, but not containing a polishing abrasive.Type: ApplicationFiled: May 20, 2003Publication date: April 7, 2005Inventors: Seiichi Kondo, Yoshio Homma, Noriyuki Sakuma, Kenichi Takeda, Kenji Hinode
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Patent number: 6864584Abstract: In extremely minute copper wiring the width or the thickness of which is equal to or shorter than approximately the double length of the mean free path of a copper atom, a value of the resistance may be larger, compared with aluminum wiring of the same extent and it is difficult to realize wiring having small resistance. To solve such a problem, aluminum wiring is used for wiring having form in which the respective resistivities ? of both wirings have the relation of ?Al<?Cu and copper wiring is used for wiring having form in which the respective resistivities ? of both wirings have the relation of ?Al??Cu. As a result, a semiconductor device which has small resistance, transmits a signal at high speed and is provided with a multilayer wiring layer can be realized.Type: GrantFiled: October 18, 2002Date of Patent: March 8, 2005Assignee: Hitachi, Ltd.Inventors: Yuko Hanaoka, Kenji Hinode, Kenichi Takeda, Daisuke Kodama, Noriyuki Sakuma
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Publication number: 20040266209Abstract: To provide a planarization method which does not depend upon the size and the density of a wiring pattern and in which a reliable wiring system and a Josephson device can be formed and wiring structure, an insulation layer is planarized by forming a reversal pattern mask of wiring and selectively removing the insulation layer on the wiring.Type: ApplicationFiled: June 24, 2004Publication date: December 30, 2004Inventors: Kenji Hinode, Shuichi Nagasawa, Yoshihiro Kitagawa, Mutsuo Hidaka, Keiichi Tanabe
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Publication number: 20040229468Abstract: A polishing technique wherein scratches, peeling, dishing and erosion are suppressed, a complex cleaning process and slurry supply/processing equipment are not required, and the cost of consumable items such as slurries and polishing pads is reduced. A metal film formed on an insulating film comprising a groove is polished with a polishing solution containing an oxidizer and a substance which renders oxides water-soluble, but not containing a polishing abrasive.Type: ApplicationFiled: April 16, 2004Publication date: November 18, 2004Inventors: Seiichi Kondo, Yoshio Homma, Noriyuki Sakuma, Kenichi Takeda, Kenji Hinode
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Patent number: 6800557Abstract: In order to provide an anticorrosive technique for metal wirings formed by a chemical mechanical polishing (CMP) method, a process for manufacturing a semiconductor integrated circuit device according to the invention comprises the steps of: forming a metal layer of Cu (or a Cu alloy containing Cu as a main component) over the major face of a wafer and then planarizing the metal layer by a chemical mechanical polishing (CMP) method to form metal wirings; anticorroding the planarized major face of the wafer to form a hydrophobic protective film over the surfaces of the metal wirings; immersing the anticorroded major face of the wafer or keeping the same in a wet state so that it may not become dry; and post-cleaning the major face, kept in the wet state, of the wafer.Type: GrantFiled: February 21, 2003Date of Patent: October 5, 2004Assignee: Renesas Technology Corp.Inventors: Naofumi Ohashi, Junji Noguchi, Toshinori Imai, Hizuru Yamaguchi, Nobuo Owada, Kenji Hinode, Yoshio Homma, Seiichi Kondo