Patents by Inventor Kenji Hinode
Kenji Hinode has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20040152298Abstract: In order to provide an anticorrosive technique for metal wirings formed by a chemical mechanical polishing (CMP) method, a process for manufacturing a semiconductor integrated circuit device according to the invention comprises the steps of: forming a metal layer of Cu (or a Cu alloy containing Cu as a main component) over the major face of a wafer and then planarizing the metal layer by a chemical mechanical polishing (CMP) method to form metal wirings; anticorroding the planarized major face of the wafer to form a hydrophobic protective film over the surfaces of the metal wirings; immersing the anticorroded major face of the wafer or keeping the same in a wet state so that it may not become dry; and post-cleaning the major face, kept in the wet state, of the wafer.Type: ApplicationFiled: January 21, 2004Publication date: August 5, 2004Inventors: Naofumi Ohashi, Junji Noguchi, Toshinori Imai, Hizuru Yamaguchi, Nobuo Owada, Kenji Hinode, Yoshio Homma, Seiichi Kondo
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Patent number: 6680541Abstract: An intermetal insulating film containing at least silicon atoms, oxygen atoms and carbon atoms with the number ratio of oxygen atom to silicon atom being 1.5 or more and the number ratio of carbon atom to silicon atom being 1 to 2, and having a film thickness shrinkage at a time of oxidation of 14% or less is very low in dielectric constant, high in selectivity against resist etching and can be used without using a silicon oxide protective film in a semiconductor device.Type: GrantFiled: January 18, 2002Date of Patent: January 20, 2004Assignees: Hitachi, Ltd., Hitachi ULSI Systems Co., Ltd.Inventors: Takeshi Furusawa, Daisuke Ryuzaki, Noriyuki Sakuma, Shuntaro Machida, Kenji Hinode, Ryou Yoneyama
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Publication number: 20030153187Abstract: In order to provide an anticorrosive technique for metal wirings formed by a chemical mechanical polishing (CMP) method, a process for manufacturing a semiconductor integrated circuit device according to the invention comprises the steps of: forming a metal layer of Cu (or a Cu alloy containing Cu as a main component) over the major face of a wafer and then planarizing the metal layer by a chemical mechanical polishing (CMP) method to form metal wirings; anticorroding the planarized major face of the wafer to form a hydrophobic protective film over the surfaces of the metal wirings; immersing the anticorroded major face of the wafer or keeping the same in a wet state so that it may not become dry; and post-cleaning the major face, kept in the wet state, of the wafer.Type: ApplicationFiled: February 21, 2003Publication date: August 14, 2003Inventors: Naofumi Ohashi, Junji Noguchi, Toshinori Imai, Hizuru Yamaguchi, Nobuo Owada, Kenji Hinode, Yoshio Homma, Seiichi Kondo
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Patent number: 6596638Abstract: A polishing technique wherein scratches, peeling, dishing and erosion are suppressed, a complex cleaning process and slurry supply/processing equipment are not required, and the cost of consumable items, such as slurries and polishing pads, is reduced. A metal film formed on an insulating film having a groove is polished with a polishing solution containing an oxidizer and a substance which renders oxides water-soluble, but not containing a polishing abrasive.Type: GrantFiled: July 18, 2000Date of Patent: July 22, 2003Assignee: Hitachi, Ltd.Inventors: Seiichi Kondo, Yoshio Homma, Noriyuki Sakuma, Kenichi Takeda, Kenji Hinode
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Publication number: 20030111730Abstract: A semiconductor device according to this invention comprises a substrate 100 in which semiconductor elements are formed, a first conductor 301 at least a portion of the peripheral surface of which is made of a material comprising copper as a main ingredient, and a first insulative diffusion barrier layer 203 covering at least a portion of the first conductor 301. The first insulative diffusion barrier layer 203 is formed by using a gas mixture at least containing an alkoxy silane represented by the general formula (RO)nSiH4−n (n is an integer in a range from 1 to 3, R represents an alkyl group, an aryl group or a derivative thereof), and an oxidative gas by a plasma CVD. Thus, a semiconductor device comprising copper wiring of high reliability and with less wiring delay time can be provided.Type: ApplicationFiled: November 19, 2002Publication date: June 19, 2003Inventors: Kenichi Takeda, Daisuke Ryuzaki, Kenji Hinode, Toshiyuki Mine
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Publication number: 20030080433Abstract: In extremely minute copper wiring the width or the thickness of which is equal to or shorter than approximately the double length of the mean free path of a copper atom, a value of the resistance may be larger, compared with aluminum wiring of the same extent and it is difficult to realize wiring having small resistance. To solve such a problem, aluminum wiring is used for wiring having form in which the respective resistivities &rgr; of both wirings have the relation of &rgr;Al<&rgr;Cu and copper wiring is used for wiring having form in which the respective resistivities &rgr; of both wirings have the relation of &rgr;Al≧&rgr;Cu. As a result, a semiconductor device which has small resistance, transmits a signal at high speed and is provided with a multilayer wiring layer can be realized.Type: ApplicationFiled: October 18, 2002Publication date: May 1, 2003Inventors: Yuko Hanaoka, Kenji Hinode, Kenichi Takeda, Daisuke Kodama, Noriyuki Sakuma
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Patent number: 6531400Abstract: In order to provide an anticorrosive technique for metal wirings formed by a chemical mechanical polishing (CMP) method, a process for manufacturing a semiconductor integrated circuit device according to the invention comprises the steps of: forming a metal layer of Cu (or a Cu alloy containing Cu as a main component) over the major face of a wafer and then planarizing the metal layer by a chemical mechanical polishing (CMP) method to form metal wirings; anticorroding the planarized major face of the wafer to form a hydrophobic protective film over the surfaces of the metal wirings; immersing the anticorroded major face of the wafer or keeping the same in a wet state so that it may not become dry; and post-cleaning the major face, kept in the wet state, of the wafer.Type: GrantFiled: August 19, 2002Date of Patent: March 11, 2003Assignee: Hitachi, Ltd.Inventors: Naofumi Ohashi, Junji Noguchi, Toshinori Imai, Hizuru Yamaguchi, Nobuo Owada, Kenji Hinode, Yoshio Homma, Seiichi Kondo
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Publication number: 20020192967Abstract: In order to provide an anticorrosive technique for metal wirings formed by a chemical mechanical polishing (CMP) method, a process for manufacturing a semiconductor integrated circuit device according to the invention comprises the steps of: forming a metal layer of Cu (or a Cu alloy containing Cu as a main component) over the major face of a wafer and then planarizing the metal layer by a chemical mechanical polishing (CMP) method to form metal wirings; anticorroding the planarized major face of the wafer to form a hydrophobic protective film over the surfaces of the metal wirings; immersing the anticorroded major face of the wafer or keeping the same in a wet state so that it may not become dry; and post-cleaning the major face, kept in the wet state, of the wafer.Type: ApplicationFiled: August 19, 2002Publication date: December 19, 2002Inventors: Naofumi Ohashi, Junji Noguchi, Toshinori Imai, Hizuru Yamaguchi, Nobuo Owada, Kenji Hinode, Yoshio Homma, Seiichi Kondo
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Patent number: 6458674Abstract: In order to provide an anticorrosive technique for metal wirings formed by a chemical mechanical polishing (CMP) method, a process for manufacturing a semiconductor integrated circuit device according to the invention comprises the steps of: forming a metal layer of Cu (or a Cu alloy containing Cu as a main component) over the major face of a wafer and then planarizing the metal layer by a chemical mechanical polishing (CMP) method to form metal wirings; anticorroding the planarized major face of the wafer to form a hydrophobic protective film over the resurfaces of the metal wirings; immersing the anticorroded major face of the wafer or keeping the same in a wet state so that it may not become dry; and post-cleaning the major face, kept in the wet state, of the wafer.Type: GrantFiled: January 18, 2002Date of Patent: October 1, 2002Assignee: Hitachi, Ltd.Inventors: Naofumi Ohashi, Junji Noguchi, Toshinori Imai, Hizuru Yamaguchi, Nobuo Owada, Kenji Hinode, Yoshio Homma, Seiichi Kondo
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Publication number: 20020105085Abstract: An intermetal insulating film containing at least silicon atoms, oxygen atoms and carbon atoms with the number ratio of oxygen atom to silicon atom being 1.5 or more and the number ratio of carbon atom to silicon atom being 1 to 2, and having a film thickness shrinkage at a time of oxidation of 14% or less is very low in dielectric constant, high in selectivity against resist etching and can be used without using a silicon oxide protective film in a semiconductor device.Type: ApplicationFiled: January 18, 2002Publication date: August 8, 2002Applicant: Hitachi, Ltd.Inventors: Takeshi Furusawa, Daisuke Ryuzaki, Noriyuki Sakuma, Shuntaro Machida, Kenji Hinode, Ryou Yoneyama
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Publication number: 20020058363Abstract: In order to provide an anticorrosive technique for metal wirings formed by a chemical mechanical polishing (CMP) method, a process for manufacturing a semiconductor integrated circuit device according to the invention comprises the steps of: forming a metal layer of Cu (or a Cu alloy containing Cu as a main component) over the major face of a wafer and then planarizing the metal layer by a chemical mechanical polishing (CMP) method to form metal wirings; anticorroding the planarized major face of the wafer to form a hydrophobic protective film over the surfaces of the metal wirings; immersing the anticorroded major face of the wafer or keeping the same in a wet state so that it may not become dry; and post-cleaning the major face, kept in the wet state, of the wafer.Type: ApplicationFiled: January 18, 2002Publication date: May 16, 2002Inventors: Naofumi Ohashi, Junji Noguchi, Toshinori Imai, Hizuru Yamaguchi, Nobuo Owada, Kenji Hinode, Yoshio Homma, Seiichi Kondo
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Patent number: 6376345Abstract: In order to provide an anticorrosive technique for metal wirings formed by a chemical mechanical polishing (CMP) method, a process for manufacturing a semiconductor integrated circuit device according to the invention comprises the steps of: forming a metal layer of Cu (or a Cu alloy containing Cu as a main component) over the major face of a wafer and then planarizing the metal layer by a chemical mechanical polishing (CMP) method to form metal wirings; anticorroding the planarized major face of the wafer to form a hydrophobic protective film over the surfaces of the metal wirings; immersing the anticorroded major face of the wafer or keeping the same in a wet state so that it may not become dry; and post-cleaning the major face, kept in the wet state, of the wafer.Type: GrantFiled: July 20, 1999Date of Patent: April 23, 2002Assignee: Hitachi Ltd.Inventors: Naofumi Ohashi, Junji Noguchi, Toshinori Imai, Hizuru Yamaguchi, Nobuo Owada, Kenji Hinode, Yoshio Homma, Seiichi Kondo
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Patent number: 6358838Abstract: An intermetal insulating film containing at least silicon atoms, oxygen atoms and carbon atoms with the number ratio of oxygen atom to silicon atom being 1.5 or more and the number ratio of carbon atom to silicon atom being 1 to 2, and having a film thickness shrinkage at a time of oxidation of 14% or less is very low in dielectric constant, high in selectivity against resist etching and can be used without using a silicon oxide protective film in a semiconductor device.Type: GrantFiled: January 17, 2001Date of Patent: March 19, 2002Assignees: Hitachi, Ltd., Hitachi ULSI Systems Co., Ltd.Inventors: Takeshi Furusawa, Daisuke Ryuzaki, Noriyuki Sakuma, Shuntaro Machida, Kenji Hinode, Ryou Yoneyama
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Publication number: 20010009295Abstract: An intermetal insulating film containing at least silicon atoms, oxygen atoms and carbon atoms with the number ratio of oxygen atom to silicon atom being 1.5 or more and the number ratio of carbon atom to silicon atom being 1 to 2, and having a film thickness shrinkage at a time of oxidation of 14% or less is very low in dielectric constant, high in selectivity against resist etching and can be used without using a silicon oxide protective film in a semiconductor device.Type: ApplicationFiled: January 17, 2001Publication date: July 26, 2001Inventors: Takeshi Furusawa, Daisuke Ryuzaki, Noriyuki Sakuma, Shuntaro Machida, Kenji Hinode, Ryou Yoneyama
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Patent number: 6117775Abstract: A polishing technique wherein scratches, peeling, dishing and erosion are suppressed, a complex cleaning process and slurry supply/processing equipment are not required, and the cost of consumable items, such as slurries and polishing pads, is reduced. A metal film formed on an insulating film having a groove is polished with a polishing solution containing an oxidizer and a substance which renders oxides water-soluble, but not containing a polishing abrasive.Type: GrantFiled: October 30, 1998Date of Patent: September 12, 2000Assignee: Hitachi, Ltd.Inventors: Seiichi Kondo, Yoshio Homma, Noriyuki Sakuma, Kenichi Takeda, Kenji Hinode
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Patent number: 4897709Abstract: A semiconductor device includes a titanium nitride film as a barrier which is formed in a hole. The width or diameter of the hole is smaller than 1 .mu.m, and the aspect ratio thereof is larger than 0.7. The sidewall of the hole is substantially perpendicular to the surface of a semiconductor substrate. By the low pressure CVD method with a cold wall type CVD apparatus, it becomes possible to form the titanium nitride film having excellent characteristics with a good step coverage in a considerably fine hole having a large aspect ratio.Type: GrantFiled: May 26, 1988Date of Patent: January 30, 1990Assignee: Hitachi, Ltd.Inventors: Natsuki Yokoyama, Yoshio Homma, Kenji Hinode, Kiichiro Mukai
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Patent number: 4887146Abstract: A semiconductor device having a TiN film serving as a barrier layer and a TiN.sub.x (0.3<X<0.9) film between a wiring layer and a semiconductor substrate is disclosed. Interposition of the TiN.sub.x film between the semiconductor substrate and the TiN film lowers the contact resistance in the contact region between the semiconductor substrate and the wiring layer and also the leakage current and improves the adhesion between the wiring layer and the semiconductor substrate, so that the characteristics and reliability of the semiconductor device are greatly improved.Type: GrantFiled: May 5, 1987Date of Patent: December 12, 1989Assignee: Hitachi, Ltd.Inventor: Kenji Hinode