Abstract: A horizontal scanning frequency multiplying circuit comprises a flip-flop supplied with an input horizontal synchronizing signal having a horizontal scanning frequency f.sub.H of a television signal, a phase-locked-loop (PLL) for producing a signal having a frequency Nf.sub.

Abstract: A data regenerating circuit is included in a video disk recording and playback systems in which the video disk is controlled in a desired mode in response to selected digital control data contained in the vertical blanking intervals of a recorded video signal. The circuit includes a random noise detector for detecting noise that might occur in the vertical blanking interval to prevent the control system from operating the disk in an undesired mode.

Abstract: A data reproducing circuit comprises a modulated data signal supplying circuit for supplying a modulated data signal including a framing code representing a series of data signals, a clock signal detecting and reproducing circuit supplied with the demodulated data signal, for detecting and reproducing a clock signal, a data signal demodulating circuit supplied with the modulated data signal, for demodulating the data signal, a memory circuit for reading in and reading out a data signal demodulated by the data signal demodulating circuit, a framing code detecting circuit for detecting a framing code within a signal read in by the memory circuit, an instruction signal producing circuit responsive to the detection of the framing code by the framing code detecting circuit, for producing a signal for instructing read-out from the memory circuit, and a dropout detecting circuit for detecting dropout within the modulated data signal supplied thereto and producing a detected output, so that the instruction signal pro

Abstract: A horizontal scanning frequency multiplying circuit comprises a flip-flop supplied with a horizontal synchronizing signal having a horizontal scanning frequency f.sub.H, which is set by this horizontal synchronizing signal, a phase-locked-loop, and a counter. The phase-locked-loop comprises a voltage controlled oscillator for producing a signal having a frequency Nf.sub.H (N is an integer over 1) which is N times the horizontal scanning frequency f.sub.H, a frequency divider for frequency-dividing an output signal frequency of the voltage controlled oscillator, and a phase comparator supplied with one output signal of the flip-flop and an output signal of the frequency divider, for comparing phases of these signals and applying an output error signal to the voltage controlled oscillator to control the oscillation frequency of the voltage controlled oscillator.

Abstract: A bi-phase space code data signal reproducing circuit comprises a clock pulse supplying circuit for supplying a clock pulse having a period which is 1/N (N is an integer) of a bit period T of a bi-phase space code data signal to be reproduced, a shift register supplied with the clock pulse, for performing a shifting operation, a main flip-flop supplied with the data signal and an output signal obtained from an intermediate part of the shift register, for holding a sampling value of the data signal at a point which is substantially T/4 from the beginning of each data of the data signal, an exclusive-OR circuit supplied with an output signal of the main flip-flop and said data signal, and a reproduced data obtaining circuit for sampling an output signal of the exclusive-OR circuit by a sampling clock at a point which is substantially 3T/4 from the beginning of each data of the data signal obtained from the shift register, to obtain a reproduced data.

Abstract: A logic circuit is provided which includes a plurality of basic circuits each of which has a pnp (or npn) transistor as a constant current load and at least one npn (or pnp) transistor each as a driver with a clamping Schottky diode. The base of the driver transistor is used as an input terminal and the collector thereof is used as an output terminal, for each basic circuit and the output terminal of the preceding stage basic circuit is coupled directly to the input terminal of the subsequent stage basic circuit. In order to prevent current hogging the load current supplied from the preceding stage constant current load transistor is set to operate the subsequent stage driver transistor in a saturation made when the subsequent stage driver transistor is in the ON state.

Abstract: A rotary recording medium reproducing apparatus reproduces a rotary recording medium having a spiral video signal track recorded with a video signal by use of a reproducing element, where the recording medium further has a reference signal track between each information signal track turn alternately switched over and recorded with first and second reference signals for an interval corresponding to each track turn, and recorded with a third reference signal at a position corresponding to the position where the first and second reference signals are switched over.

Abstract: An I.sup.2 L type nonvolatile memory of this invention has a structure wherein a floating gate is disposed through an insulating film on the surface of a semiconductor layer in the vicinity of a base region of an NPN transistor in an I.sup.2 L. The I.sup.2 L type nonvolatile memory of this invention controls current to flow through the base region of the NPN transistor of the I.sup.2 L, by means of charges to be stored in the floating gate. That is, the collector output current of the NPN transistor of the I.sup.2 L is modulated in dependence on the presence or absence of a channel underneath the floating gate as is generated depending on the presence or absence of charges within the floating gate and the polarity of the charges. As a result, the variation of the base current appears as an output signal at a collector terminal of the NPN transistor of the I.sup.2 L, and data stored in the floating gate can be read out.

Abstract: A PCM signal extracting circuit comprises a highpass filter for separating a PCM signal, of a type not including a DC component, inserted between horizontal synchronizing signals within a predetermined interval of a composite video signal or a signal based on the composite video signal, and for obtaining an average DC level of the horizontal synchronizing signal and the PCM signal, an attenuation circuit for attenuating an output signal of the highpass filter by a predetermined quantity according to the modulation factor of the PCM signal, a holding circuit for holding a peak value, at the opposite side from the horizontal synchronizing signal, of the signal attenuated by the attenuation circuit, and a level comparing circuit for comparing the levels of output signals of the highpass filter and the holding circuit, and extracting a signal obtained by slicing the output signal of the highpass filter by the level of the output signal of the holding circuit.

Abstract: An oscillation circuit including an amplifier portion wherein the collector of a first switching transistor has a load connected thereto, means is provided for transmitting an output of the collector of the first switching transistor to the base thereof, means is provided for transmitting the output of the collector of the first switching transistor to the base of a second switching transistor, and the collector of the second switching transistor has a load connected thereto. A capacitive element is connected between the collector of the second switching transistor and the base of the first switching transistor of the amplifier portion so as to feedback an output of the second switching transistor to the first switching transistor to operate the circuit as an oscillator.

Abstract: A differential amplifier circuit wherein one collector of the multicollector of each of first, second and third inverse NPN transistors is connected to a base of the corresponding transistor; the first and second transistors are used as differential input transistors; the other collector of each of the first and second transistors is connected to a PNP transistor serving as a load current source; and an output is derived through the third transistor connected to the second transistor.

Abstract: A semiconductor IC device in which an N-type semiconductor layer is formed in a P-type semiconductor substrate; the N-type layer is divided by a P.sup.+ -type insulation region into plural island regions; and an IIL is formed in a first island region while an NPN transistor is formed in a second island region, wherein an N-type up-diffused layer is formed from the bottom of the first island region up while an N-type well region is formed from the surface of the first island region down, and N.sup.+ -type buried layers are formed near the bottoms of the first and the second island region.

Abstract: An oscillation circuit including an amplifier portion wherein the collector of a first switching transistor has a load connected thereto, means is provided for transmitting an output of the collector of the first switching transistor to the base thereof, means is provided for transmitting the output of the collector of the first switching transistor to the base of a second switching transistor, and the collector of the second switching transistor has a load connected thereto. A capacitive element is connected between the collector of the second switching transistor and the base of the first switching transistor of the amplifier portion so as to feedback an output of the second switching transistor to the first switching transistor to operate the circuit as an oscillator.

Abstract: An electron device comprising (i) a semiconductor element which includes a semiconductor region A of a first conductivity type, a semiconductor region B of a second conductivity type adjoining the region A, and a semiconductor region C of the second conductivity type adjoining the region A and isolated from the region B by the region A, and in which on a surface extending from the region B via the region A to the region C, a gate electrode is provided through an insulating film, (ii) means for holding a potential of the gate electrode so that a potential of minority carriers in a surface portion of the region A underneath the gate electrode may become lower than a potential in an inner portion of the region A, (iii) means for applying a forward bias voltage between the region A and the region B, and (iv) means for applying to the region C a potential by which a potential for the minority carriers becomes lower in the region C than in the region B.

Abstract: A flip-flop circuit comprises a pair of inversely operated first and second npn vertical transistors. The first npn transistor has dual collectors. Also provided are a pair of first and second pnp lateral transistors operated as loads and a pair of third and fourth pnp lateral transistors for triggering, each base of the first and second npn vertical transistors being connected to a collector of the second npn transistor and to one of the dual collectors of the first npn transistor, respectively. Each collector of the first and second pnp transistors is connected to said one of the dual collectors of the first npn transistor and to the collector of the second npn transistor, respectively.