Abstract: A first distributed processing node transmits distributed data to a second distributed processing node as intermediate consolidated data. A third distributed processing node generates intermediate consolidated data after update from received intermediate consolidated data and distributed data, and transmits the intermediate consolidated data to a fourth distributed processing node. The first distributed processing node transmits the received intermediate consolidated data to fifth distributed processing node as consolidated data. The third distributed processing node transmits the received consolidated data to a sixth distributed processing node.

Abstract: A distributed deep learning system includes a plurality of computers connected to each other over a communication network, wherein each iteratively performs forward propagation calculation and backpropagation calculation based on learning data, and sends a calculation result of the backpropagation calculation to the communication network, and an Allreduce processing apparatus connected to the computers over the communication network, that processes the calculation results received from the plurality of computers, and returns the calculation results to transmission sources, wherein the computers each include a forward propagation calculator, a backpropagation calculator, a transfer processor that stores the calculation result of the backpropagation calculation in a transfer buffer each time the backpropagation calculator calculates the calculation result of the backpropagation calculation for each of layers, and a communicator that sequentially transmits the calculation results of the backpropagation calculati

Abstract: A distributed processing system includes a plurality of lower-order aggregation networks and a higher-order aggregation network. The lower-order aggregation networks include a plurality of distributed processing nodes disposed in a ring form. The distributed processing nodes generate distributed data for each weight of a neural network of an own node. The lower-order aggregation networks aggregate, for each lower-order aggregation network, the distributed data generated by the distributed processing nodes. The higher-order aggregation network generates aggregated data where the aggregation results of the lower-order aggregation networks are further aggregated, and distributes to the lower-order aggregation networks. The lower-order aggregation networks distribute the aggregated data distributed thereto to the distributed processing nodes belonging to the same lower-order aggregation network. The distributed processing nodes update weights of the neural network based on the distributed aggregated data.

Abstract: Individual distributed processing nodes packetize distributed data for each weight of a neural network of a learning object in an order of a number of the weight, transmit the distributed data to an aggregation processing node, acquire aggregation data transmitted from the node in order, and update the weight of the neural network. The node acquires the transmitted distributed data, packetizes the aggregation data for which the distributed data of all the distributed processing nodes is aggregated for each weight, and transmits the aggregation data to the individual nodes. The individual nodes monitor an unreceived data amount which is a difference between data amounts of the transmitted distributed data and the acquired aggregation data, and when the unreceived data amount becomes equal to or larger than a threshold Ma, stops transmission of the distributed data until the unreceived data amount becomes equal to or smaller than a threshold Mb (Mb<Ma).

Abstract: A distributed deep learning system that can achieve speeding-up by processing learning in parallel at a large number of learning nodes connected with a communication network and perform faster cooperative processing among the learning nodes connected through the communication network is provided. The distributed deep learning system includes: a plurality of computing interconnect devices 1 connected with each other through a ring communication network 3 through which communication is possible in one direction; and a plurality of learning nodes 2 connected with the respective computing interconnect devices 1 in a one-to-one relation, and each computing interconnect device 1 executes communication packet transmission-reception processing between the learning nodes 2 and All-reduce processing simultaneously in parallel.

Abstract: A first distributed processing node sets, as intermediate aggregated data, distributed data generated by the own node and transmits this data to the distributed processing node having the next number designated in advance. The intermediate distributed processing node excluding the first and last distributed processing nodes calculates, for each of weights corresponding thereto, a sum of the received intermediate aggregated data and distributed data generated by the own node, generates intermediate aggregated data after update, and transmits this data to the distributed processing node having the next number designated in advance. The last distributed processing node calculates, for each of the weights corresponding thereto, a sum of the received intermediate aggregated data and distributed data generated by the own node, generates aggregated data, and transmits this data to the first and intermediate distributed processing nodes.

Abstract: An OLT (10) is provided with a priority control bypass circuit (16) and an encryption/decryption bypass circuit (17), or an ONU (20) is provided with a priority control bypass circuit (26) and an encryption/decryption bypass circuit (27), and one or both of encryption/decryption processing and priority control processing are bypassed in accordance with a priority control bypass instruction (BP) and an encryption/decryption bypass instruction (BE), which are set in advance. This reduces a processing delay that occurs in the OLT or the ONU.

Abstract: Each of distributed processing nodes [n] (n=1, . . . , and N) packetizes pieces of distributed data [m, n] as packets for every M weights w [m] ((m=1, . . . , and M) of a neural network to be learned in an order of numbers m, transmits the packets to a consolidation processing node, receives a packet transmitted from the consolidation processing node to acquire consolidated data R [m] in the order of numbers m and update the weights w [m] of the neural network on the basis of the consolidated data R [m].

Abstract: An arithmetic circuit includes an LUT generation circuit (1) that, when coefficients c[n] (n=1, . . . , N) are paired two by two, outputs a value calculated for each of the pairs, and a distributed arithmetic circuit (2-m) that calculates values y[m] of product-sum arithmetic, by which data x[m, n] of a data set X[m] containing M pairs of data x[m, n] is multiplied by the coefficients c[n] and the products are summed up, in parallel for each of the M pairs.

Abstract: An arithmetic circuit includes an LUT generation circuit (1) that, when coefficients c[n] (n=1, . . . , N) are paired two by two, outputs a value calculated for each of the pairs, and distributed arithmetic circuits (2-m) that calculate values z[m] of product-sum arithmetic, by which data x[m, n] of a data set X[m] containing M pairs of data x[m, n] are multiplied by the coefficients c[n] and the products are summed up, in parallel for each of the M pairs.

Abstract: Each of learning nodes calculates a gradient of a loss function from an output result obtained when learning data is input to a neural network to be learned, generates a packet for a plurality of gradient components, and transmits the packet to the computing interconnect device. The computing interconnect device acquires the values of a plurality of gradient components stored in the packet transmitted from each of the learning nodes, performs a calculation process in which configuration values of gradients with respect to the same configuration parameter of the neural network are input on each of a plurality of configuration values of each gradient in parallel, generates a packet for the calculation results, and transmits the packet to each of the learning nodes. Each of the learning nodes updates the configuration parameters of the neural network based on the value stored in the packet.

Abstract: Each of learning nodes calculates gradients of a loss function from an output result obtained by inputting learning data to a learning target neural network, converts a calculation result into a packet, and transmits the packet to a computing interconnect device. The computing interconnect device receives the packet transmitted from each of the learning nodes, acquires a value of the gradients stored in the packet, calculates a sum of the gradients, converts a calculation result into a packet, and transmits the packet to each of the learning nodes. Each of the learning nodes receives the packet transmitted from the computing interconnect device and updates a constituent parameter of a neural network based on a value stored in the packet.

Abstract: A resin composition includes (A) a polyolefin epoxy resin, (B) an epoxy resin having a condensed polycyclic aromatic hydrocarbon, (C) a nitrogen-containing novolak resin, and (D) an inorganic filler, in which an epoxy equivalent of the (A) component is 200 g/eq. or more, a nitrogen content in the (C) component is 13% by mass or more and/or the (C) component has a cresol novolak structure, and a content of the (D) component is 60% by mass or more on the basis of 100% by mass of non-volatile components in the resin composition.

Abstract: An optical deflector capable of making a swing angle of a reflective plate larger is provided. In drive elements, since a size in the Y direction at first positions separated by a first distance from the reflective plate is larger than a size in the Y direction at second positions separated by a second distance from the reflective plate, the second distance being greater than the first distance, it is possible to increase displacement of tips of beam portions at the first positions and to make a swing angle of the reflective plate large by increasing a generated force of the entire beam portions.

Abstract: A stator includes first exterior members that surround sides of outer circumferential portions of coil ends on both end sides of an iron core, second exterior members connected to the first exterior members, and which surround sides of end portions of the coil ends in the axial direction, and mold members that cover the coil ends and are placed in contact with the first exterior members and the second exterior members. Holes are formed in the second exterior member on one end side, and a surface that faces the mold member, of the second exterior member on the one end side, is inclined in a manner so that a thickness thereof becomes continuously thinner toward the holes.

Abstract: An antenna apparatus includes a first antenna that is arranged within a predetermined area on a dielectric substrate and receives a radio wave in a first frequency band, a second antenna that is arranged in a position within the predetermined area different from the first antenna and receives a radio wave in a second frequency band, and a third antenna that is arranged in a position within the predetermined area different from the first antenna and different from the second antenna and receives a radio wave in a third frequency band. An area of the predetermined area is smaller than a sum of a minimum rectangular area including the first antenna, a minimum rectangular area including the second antenna and a minimum rectangular area including the third antenna.

Abstract: An antenna apparatus includes a dielectric substrate, a first antenna element that is arranged within a predetermined area on the dielectric substrate and receives a first radio wave in a first frequency band, and a second antenna element that is arranged in a portion within the predetermined area in which the first antenna element is not arranged and receives a second radio wave in a second frequency band. The first antenna element is contained within a first rectangular area, and the first rectangular area is a smallest rectangle that circumscribes the first antenna element. The second antenna element is contained within a second rectangular area, and the second rectangular area is a smallest rectangle that circumscribes the second antenna element. An area of the predetermined area is smaller than a sum of areas of the first rectangular area and the second rectangular area.

Abstract: A rotor capable of suppressing cogging torque and heat build-up caused when an electric motor is operated. The rotor includes a sleeve fixed to a radially outside of a rotary shaft, a plurality of magnets disposed around a radially outside of the sleeve, and a reinforcing member having a cylindrical shape that surrounds the plurality of magnets while being in contact with an outer surface of each of the plurality of magnets to hold the plurality of magnets with the sleeve, each of the plurality of magnets including a central portion in a circumferential direction, in contact with the sleeve, and an end portion in the circumferential direction, having a thickness less than that of the central portion and forming a gap with the sleeve.

Abstract: A protection device provided between a synchronous motor having a plurality of windings and a motor driving device for driving the synchronous motor includes: a switching unit for making and breaking the connection between the motor driving device and the synchronous motor; a dynamic brake circuit including resistors and switches, to short-circuit the plurality of windings between the switching unit and the synchronous motor via the resistors; and a control device for controlling the switching unit and the dynamic brake circuit. The control device controls the switches in the dynamic brake circuit to short-circuit the plurality of windings, and then controls the switching unit to cut off the connection between the motor driving device and the synchronous motor.

Abstract: An amplifier circuit includes a first transistor, a second transistor, a first pathway and a second pathway. The first transistor amplifies an external signal that is input from outside the amplifier circuit. The second transistor amplifies a detection signal that detects a level of the external signal. The first pathway is connected between a collector of the first transistor and a base of the second transistor to supply the detection signal that is output from the collector of the first transistor to the base of the second transistor. The second pathway is connected between an emitter of the first transistor and the base of the second transistor to supply a bias voltage from the emitter of the first transistor to the base of the second transistor.