Patents by Inventor Kenji Kobae

Kenji Kobae has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20100327435
    Abstract: An electronic component includes a package substrate, a plurality of conductive pads, an insulating material and a semiconductor device. The plurality of conductive pads is disposed on the package substrate. The insulating material is disposed between the plurality of conductive pads. The insulating material includes a top surface located on an identical plane to an upper surface of the plurality of conductive pads. The semiconductor device includes a conductive bump aligned on a corresponding conductive pad of the plurality of conductive pads.
    Type: Application
    Filed: June 24, 2010
    Publication date: December 30, 2010
    Applicant: FUJITSU LIMITED
    Inventors: Kimio Nakamura, Takayoshi Matsumura, Yoshiyuki Satoh, Kuniko Ishikawa, Kenji Kobae
  • Publication number: 20100328917
    Abstract: A multichip module includes a package substrate, a first semiconductor device, a second semiconductor device and a conductive bump. The first semiconductor device is flip-chip bonded to the package substrate. The first semiconductor device includes a first chip pad on a surface thereof. The second semiconductor device is mounted on the first semiconductor device. The second semiconductor device includes a second chip pad facing the first chip pad. The conductive bump connects the first chip pad to the second chip pad. The conductive bump includes a first metallic body that has a first diffusion rate and a second metallic body that has a second diffusion rate lower than the first diffusion rate.
    Type: Application
    Filed: June 23, 2010
    Publication date: December 30, 2010
    Applicant: FUJITSU LIMITED
    Inventors: Takayoshi MATSUMURA, Kenji Kobae, Shuichi Takeuchi, Tetsuya Takahashi
  • Publication number: 20100327043
    Abstract: A compression-bonding apparatus includes a support stage and a pressing tool. The pressing tool includes a pressing stage, an elastic member and a plurality of bonding heads. The elastic member is held by the pressing stage. The plurality of bonding heads includes an upper surface attached to the elastic member and a lower surface facing an upper surface of the support stage.
    Type: Application
    Filed: June 18, 2010
    Publication date: December 30, 2010
    Applicant: FUJITSU LIMITED
    Inventors: Kimio NAKAMURA, Yoshiyuki Satoh, Kenji Kobae
  • Publication number: 20100258640
    Abstract: An RFID tag includes an inlet on which an antenna pattern serving as an antenna for communication and an IC chip electrically connected to the antenna pattern are mounted. The RFID tag also includes an exterior body that encloses the inlet from outside and a hollow space that is formed by the inlet and the exterior body and that is filled with gas or a gel material.
    Type: Application
    Filed: April 8, 2010
    Publication date: October 14, 2010
    Applicant: FUJITSU LIMITED
    Inventors: Shuichi Takeuchi, Kenji Kobae, Takayoshi Matsumura, Tetsuya Takahashi
  • Publication number: 20100243743
    Abstract: A radio frequency identification tag is provided. The radio frequency identification tag includes a base, an antenna formed on the base, an integrated circuit chip electrically connected to the antenna, and a bonding layer bonding the integrated circuit chip to the base. The bonding layer includes a conductive filler. The base is configured to bend away from a surface on which the integrated circuit chip is bonded.
    Type: Application
    Filed: March 12, 2010
    Publication date: September 30, 2010
    Applicant: FUJITSU LIMITED
    Inventors: Shuichi TAKEUCHI, Kenji KOBAE, Takayoshi MATSUMURA, Tetsuya TAKAHASHI
  • Patent number: 7789316
    Abstract: An electronic device includes: a base; a conductor pattern formed on the base; a circuit chip electrically connected to the conductor pattern; and a reinforcing member which is disposed on the base to surround the circuit chip, whose outer shape is like a ring, and which has such an internal structure that a plurality of columns extending in the thickness direction of the base are dispersed in a predetermined substrate. The electronic device further includes a sealing member which fills an inside of the reinforcing member while covering the top of the circuit chip, thereby sealing the circuit chip on the base.
    Type: Grant
    Filed: September 14, 2009
    Date of Patent: September 7, 2010
    Assignee: Fujitsu Limited
    Inventors: Hiroshi Kobayashi, Kenji Kobae, Shuichi Takeuchi, Hidehiko Kira
  • Patent number: 7712650
    Abstract: When a semiconductor chip is mounted using ultrasonic vibration, a method of mounting makes it possible to bond the semiconductor chip and bonding patterns with sufficient bonding strength without making the construction of a circuit board complex. The method of mounting a semiconductor chip causes ultrasonic vibration to act on the semiconductor chip to mount the semiconductor chip on a circuit board by flip-chip bonding. As the circuit board, a circuit board is used where protrusion patterns are provided at positions on bonding patterns to which the semiconductor chip is bonded corresponding to antinodes of vibration for a case where the bonding patterns resonate due to ultrasonic vibration applied by the semiconductor chip.
    Type: Grant
    Filed: February 17, 2006
    Date of Patent: May 11, 2010
    Assignee: Fujitsu Limited
    Inventors: Takayoshi Matsumura, Kenji Kobae, Norio Kainuma, Kimio Nakamura
  • Patent number: 7687314
    Abstract: An electronic apparatus manufacturing method comprises applying a first adhesive agent to a mounting portion, a first heating, in such a way that connection pads and bumps, come into contact, by pressing a heating head against a non-mounting surface of the electronic component, heating the electronic component, hardening the first adhesive agent, affixing the mounting substrate and electronic component, filling a space between the mounting substrate and the electronic component with a second adhesive agent under reduced pressure, and a second heating step of, from being under reduced pressure to being under atmospheric pressure, by pressing the heating head against the non-mounting surface of the electronic component, heating the electronic component, as well as hardening the second adhesive agent, melting the connection pads, and joining the connection pads and the bumps.
    Type: Grant
    Filed: December 8, 2008
    Date of Patent: March 30, 2010
    Assignee: Fujitsu Limited
    Inventors: Shuichi Takeuchi, Hidehiko Kira, Kenji Kobae, Yoshiyuki Satoh, Tetsuya Takahashi
  • Publication number: 20100075493
    Abstract: A manufacturing method for an electrode connecting portion includes covering an electrode forming surface with a solder sheet, rolling a heating roller on the solder sheet that covers the electrode forming surface, and removing the solder sheet after the heating roller has passed over the solder sheet.
    Type: Application
    Filed: September 17, 2009
    Publication date: March 25, 2010
    Applicant: FUJITSU LIMITED
    Inventors: Kuniko Ishikawa, Norio Kainuma, Kenji Kobae
  • Publication number: 20100051703
    Abstract: A radio frequency identification tag includes a substrate, and an antenna pattern disposed on an outer peripheral side surface of the substrate. An electronic device is electrically connected to the antenna pattern, and is mounted on the outer peripheral side surface of the substrate.
    Type: Application
    Filed: July 15, 2009
    Publication date: March 4, 2010
    Inventor: Kenji KOBAE
  • Patent number: 7670873
    Abstract: A method of flip-chip mounting can reliably and stably mount a semiconductor chip to a mounting substrate while avoiding problems such as damage to the semiconductor chip due to a difference in thermal expansion coefficients between the semiconductor chip and the mounting substrate. The method of flip-chip mounting a semiconductor chip supports a mounting substrate on a stage in a state where a resin material has been supplied onto a chip mounting surface of the mounting substrate and presses the semiconductor chip toward the mounting substrate using a pressure/heat applying head to bond the semiconductor chip to the mounting substrate and thermally harden the resin material. A concave part is provided in a support surface of the stage that supports the semiconductor chip, and the semiconductor chip is bonded to the mounting substrate by pressing the semiconductor chip toward the mounting substrate using the pressure/heat applying head in a state where the mounting substrate is bent toward the concave part.
    Type: Grant
    Filed: May 18, 2006
    Date of Patent: March 2, 2010
    Assignee: Fujitsu Limited
    Inventors: Kimio Nakamura, Kenji Kobae, Takashi Kubota
  • Publication number: 20100001081
    Abstract: An electronic device includes: a base; a conductor pattern formed on the base; a circuit chip electrically connected to the conductor pattern; and a reinforcing member which is disposed on the base to surround the circuit chip, whose outer shape is like a ring, and which has such an internal structure that a plurality of columns extending in the thickness direction of the base are dispersed in a predetermined substrate. The electronic device further includes a sealing member which fills an inside of the reinforcing member while covering the top of the circuit chip, thereby sealing the circuit chip on the base.
    Type: Application
    Filed: September 14, 2009
    Publication date: January 7, 2010
    Applicant: FUJITSU LIMITED
    Inventors: Hiroshi Kobayashi, Kenji Kobae, Shuichi Takeuchi, Hidehiko Kira
  • Publication number: 20100001387
    Abstract: An electronic device includes: a base; a conductor pattern formed on the base; and a circuit chip electrically connected to the conductor pattern. The electronic device further includes a reinforcing member which is disposed on the base to surround the circuit chip, whose outer shape is like a ring, and which includes layers stacked in the thickness direction of the base. The lowermost layer of the layers is closest to the base and softer than the layer that is at least one of the remaining layers. The electronic device further includes a sealing member which fills an inside of the reinforcing member while covering the top of the circuit chip, thereby sealing the circuit chip on the base.
    Type: Application
    Filed: September 14, 2009
    Publication date: January 7, 2010
    Applicant: FUJITSU LIMITED
    Inventors: Hiroshi Kobayashi, Kenji Kobae, Shuichi Takeuchi, Hidehiko Kira
  • Publication number: 20100001388
    Abstract: An electronic device includes: a base; a conductor pattern formed on the base; a circuit chip electrically connected to the conductor pattern; and a reinforcing member which is disposed on the base to surround the circuit chip, whose outer shape is like a ring, and which includes concentric rings as an internal structure. The electronic device further includes a sealing member which fills an inside of the reinforcing member while covering the top of the circuit chip, thereby sealing the circuit chip on the base.
    Type: Application
    Filed: September 14, 2009
    Publication date: January 7, 2010
    Applicant: FUJITSU LIMITED
    Inventors: Hiroshi Kobayashi, Kenji Kobae, Shuichi Takeuchi, Hidehiko Kira
  • Publication number: 20090243062
    Abstract: An IC tag comprises a substrate on which a wiring pattern is formed, an IC chip which is bonded and mounted to the substrate by bringing a bump into press-contact with the wiring pattern, a repulsive member that is arranged on the surface opposite to the surface of the substrate on which surface the IC chip is mounted, and that is made of a material having higher rigidity than the substrate, and an exterior package member which is configured to cover the substrate, the IC chip, and the repulsive member.
    Type: Application
    Filed: March 16, 2009
    Publication date: October 1, 2009
    Applicant: FUJITSU LIMITED
    Inventors: Shuichi TAKEUCHI, Kenji KOBAE
  • Publication number: 20090243006
    Abstract: According to an aspect of the invention, an electronic part includes a substrate having a first planar surface, a first bump affixed to the first planar surface of the substrate, a second bump affixed to the first planar surface of the substrate a predetermined distance from the first bump, a MEMS chip including a element, the MEMS chip coupled to the first bump and the second bump, the MEMS chip distanced from the first planar surface, an adhesive region bonding with the first bump, the substrate and the MEMS chip.
    Type: Application
    Filed: March 12, 2009
    Publication date: October 1, 2009
    Applicant: FUJITSU Limited
    Inventors: Tetsuya TAKAHASHI, Kenji Kobae, Shuichi Takeuchi, Yoshiyuki Satoh, Hidehiko Kira, Takayoshi Matsumura
  • Publication number: 20090236127
    Abstract: An electronic device comprises a substrate; a wiring pattern which is provided on a front surface of the substrate, and which includes a plurality of connection ends; a circuit component which houses a circuit, and which includes bumps, electrically connected to the circuit, that project from a specific surface of the circuit component, and which is disposed with the specific surface facing the front surface of the substrate; conductive members which electrically connect the bumps of the circuit component and the connection ends of the wiring pattern, and which fix the circuit component to the substrate; and guide sections which are provided on the substrate, and to each of which the conductive member forced out of an interval above the corresponding connection end is guided to prevent the conductive member from reaching a connection end other than the corresponding connection end.
    Type: Application
    Filed: March 23, 2009
    Publication date: September 24, 2009
    Applicant: FUJITSU LIMITED
    Inventor: Kenji KOBAE
  • Patent number: 7582553
    Abstract: The method of bonding flying leads is capable of efficiently supersonic-bonding the flying leads to pads of a board and improving bonding reliability therebetween. The method comprises the steps of: mechanically processing the board so as to form projections, which act as margins for deformation, in boding faces of the pads, on each of which the flying lead will be bonded, positioning the flying leads to correspond to the pads; and applying supersonic vibrations to a bonding tool so as to deform and crush the projections, whereby the flying leads are respectively bonded to the pads.
    Type: Grant
    Filed: February 23, 2006
    Date of Patent: September 1, 2009
    Assignee: Fujitsu Limited
    Inventors: Takashi Kubota, Kenji Kobae, Kimio Nakamura
  • Patent number: 7566586
    Abstract: A method of manufacturing a semiconductor device flip-chip bonds electrode terminals of a substrate and a semiconductor chip together by solid-phase diffusion and underfills a gap between the substrate and the semiconductor chip with a thermosetting resin without the bonds between the terminals breaking due to heat in an underfill hardening step. The method includes a bonding step of flip-chip bonding the electrode terminals of the substrate and the semiconductor chip by solid-phase diffusion, an underfill filling step of filling the gap between the substrate and the semiconductor chip with the underfill material, and the underfill hardening step where the underfill material is heated to the hardening temperature to harden the underfill material. During the underfill hardening step, a member with a lower coefficient of thermal expansion out of the substrate and the semiconductor chip is heated to a higher temperature than the other member.
    Type: Grant
    Filed: December 6, 2006
    Date of Patent: July 28, 2009
    Assignee: Fujitsu Limited
    Inventors: Norio Kainuma, Hidehiko Kira, Kenji Kobae, Kimio Nakamura, Kuniko Ishikawa, Yukio Ozaki
  • Publication number: 20090170245
    Abstract: An electronic apparatus manufacturing method comprises applying a first adhesive agent to a mounting portion, a first heating, in such a way that connection pads and bumps, come into contact, by pressing a heating head against a non-mounting surface of the electronic component, heating the electronic component, hardening the first adhesive agent, affixing the mounting substrate and electronic component, filling a space between the mounting substrate and the electronic component with a second adhesive agent under reduced pressure, and a second heating step of,, from being under reduced pressure to being under atmospheric pressure, by pressing the heating head against the non-mounting surface of the electronic component, heating the electronic component, as well as hardening the second adhesive agent, melting the connection pads, and joining the connection pads and the bumps.
    Type: Application
    Filed: December 8, 2008
    Publication date: July 2, 2009
    Applicant: Fujitsu Limited
    Inventors: Shuichi TAKEUCHI, Hidehiko Kira, Kenji Kobae, Yoshiyuki Satoh, Tetsuya Takahashi