Patents by Inventor Kenji Konomi

Kenji Konomi has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20210296255
    Abstract: According to one embodiment, a memory device includes: a first layer stack provided in a first area of a substrate; second and third layer stacks provided in a second area of the substrate; a memory cell provided in the first layer stack; a first mark portion provided in the second layer stack; a second mark portion provided in the third layer stack; and a first portion provided between the second layer stack and the third layer stack.
    Type: Application
    Filed: February 1, 2021
    Publication date: September 23, 2021
    Applicant: Kioxia Corporation
    Inventor: Kenji KONOMI
  • Patent number: 10276459
    Abstract: According to one embodiment, there is provided a measurement method. The method includes acquiring layer information related to a plurality of layers to be superimposed for each of a plurality of shot regions on a substrate. The method includes dividing the plurality of shot regions into a plurality of groups corresponding to a layer attribute based on the acquired layer information. The method includes deciding a measurement condition of a measuring apparatus for each of the plurality of groups. The plurality of layers are sequentially stacked on the substrate to manufacture a semiconductor device.
    Type: Grant
    Filed: September 8, 2017
    Date of Patent: April 30, 2019
    Assignee: Toshiba Memory Corporation
    Inventors: Kenji Konomi, Manabu Takakuwa
  • Publication number: 20180269116
    Abstract: According to one embodiment, there is provided a measurement method. The method includes acquiring layer information related to a plurality of layers to be superimposed for each of a plurality of shot regions on a substrate. The method includes dividing the plurality of shot regions into a plurality of groups corresponding to a layer attribute based on the acquired layer information. The method includes deciding a measurement condition of a measuring apparatus for each of the plurality of groups. The plurality of layers are sequentially stacked on the substrate to manufacture a semiconductor device.
    Type: Application
    Filed: September 8, 2017
    Publication date: September 20, 2018
    Applicant: Toshiba Memory Corporation
    Inventors: Kenji KONOMI, Manabu TAKAKUWA
  • Patent number: 10040219
    Abstract: According to one embodiment, a mold includes a base, a first concave pattern, a second concave pattern, and a third concave pattern. The base includes a first surface and a pedestal projecting from the first surface. The pedestal includes a first region and a second region disposed outside the first region. The first concave pattern is formed in the first region. The second concave pattern is formed in the second region. The third concave pattern extends from the first region to the second region.
    Type: Grant
    Filed: August 30, 2013
    Date of Patent: August 7, 2018
    Assignee: TOSHIBA MEMORY CORPORATION
    Inventors: Yoko Takekawa, Ryouichi Inanami, Masafumi Asano, Kazuhiro Takahata, Sachiko Kobayashi, Shigeki Nojima, Yohko Furutono, Masato Suzuki, Kenji Konomi
  • Patent number: 10026698
    Abstract: According to one embodiment, there is provided a manufacturing method of a semiconductor device. The method includes forming a first guard ring around a first chip region on a semiconductor wafer. The method includes forming a second guard ring around a second chip region on the semiconductor wafer. The method includes mechanically connecting the first guard ring with the second guard ring through a joist structure.
    Type: Grant
    Filed: October 2, 2017
    Date of Patent: July 17, 2018
    Assignee: TOSHIBA MEMORY CORPORATION
    Inventor: Kenji Konomi
  • Patent number: 9881121
    Abstract: According to one embodiment, an inscribed figure as circle or an oval inscribed in a rectangular pattern of designed layout data is calculated, a difference in area between a lithographic shape corresponding to the rectangular pattern and the inscribed figure is calculated, and it is determined whether the difference in area satisfies a predetermined specification.
    Type: Grant
    Filed: December 28, 2015
    Date of Patent: January 30, 2018
    Assignee: TOSHIBA MEMORY CORPORATION
    Inventor: Kenji Konomi
  • Publication number: 20180025995
    Abstract: According to one embodiment, there is provided a manufacturing method of a semiconductor device. The method includes forming a first guard ring around a first chip region on a semiconductor wafer. The method includes forming a second guard ring around a second chip region on the semiconductor wafer. The method includes mechanically connecting the first guard ring with the second guard ring through a joist structure.
    Type: Application
    Filed: October 2, 2017
    Publication date: January 25, 2018
    Applicant: TOSHIBA MEMORY CORPORATION
    Inventor: Kenji KONOMI
  • Patent number: 9812403
    Abstract: A manufacturing method of a semiconductor device that can reduce warpage during wafer processing. The method includes forming a first guard ring around a first chip region on a semiconductor wafer. The method includes forming a second guard ring around a second chip region on the semiconductor wafer. The method includes mechanically connecting the first guard ring with the second guard ring through a joist structure.
    Type: Grant
    Filed: August 24, 2015
    Date of Patent: November 7, 2017
    Assignee: TOSHIBA MEMORY CORPORATION
    Inventor: Kenji Konomi
  • Publication number: 20170068770
    Abstract: According to one embodiment, an inscribed figure as circle or an oval inscribed in a rectangular pattern of designed layout data is calculated, a difference in area between a lithographic shape corresponding to the rectangular pattern and the inscribed figure is calculated, and it is determined whether the difference in area satisfies a predetermined specification.
    Type: Application
    Filed: December 28, 2015
    Publication date: March 9, 2017
    Applicant: Kabushiki Kaisha Toshiba
    Inventor: Kenji KONOMI
  • Publication number: 20160268217
    Abstract: According to one embodiment, there is provided a manufacturing method of a semiconductor device. The method includes forming a first guard ring around a first chip region on a semiconductor wafer. The method includes forming a second guard ring around a second chip region on the semiconductor wafer. The method includes mechanically connecting the first guard ring with the second guard ring through a joist structure.
    Type: Application
    Filed: August 24, 2015
    Publication date: September 15, 2016
    Applicant: Kabushiki Kaisha Toshiba
    Inventor: Kenji KONOMI
  • Patent number: 9079602
    Abstract: A steering system including a steering member provided in a vehicle and configured to be rotated, an adjustment apparatus configured to adjust a rotary direction vibration of the steering member, and a steering control apparatus configured to control the adjustment apparatus, in accordance with an operating condition of the vehicle, so as to adjust the vibration.
    Type: Grant
    Filed: May 20, 2011
    Date of Patent: July 14, 2015
    Assignee: TOYOTA JIDOSHA KABUSHIKI KAISHA
    Inventors: Kenji Konomi, Yuji Ebihara
  • Publication number: 20140284846
    Abstract: According to one embodiment, a mold includes a base, a first concave pattern, a second concave pattern, and a third concave pattern. The base includes a first surface and a pedestal projecting from the first surface. The pedestal includes a first region and a second region disposed outside the first region. The first concave pattern is formed in the first region. The second concave pattern is formed in the second region. The third concave pattern extends from the first region to the second region.
    Type: Application
    Filed: August 30, 2013
    Publication date: September 25, 2014
    Applicant: KABUSHIKI KAISHA TOSHIBA
    Inventors: Yoko TAKEKAWA, Ryouichi INANAMI, Masafumi ASANO, Kazuhiro TAKAHATA, Sachiko KOBAYASHI, Shigeki NOJIMA, Yohko FURUTONO, Masato SUZUKI, Kenji KONOMI
  • Patent number: 8785329
    Abstract: In a method for forming a pattern according to an embodiment, a first guide pattern and a second guide pattern for induced self organization of a DSA material are formed on substrate. On a first DSA condition, a first phase-separated pattern having regularity with respect to the first guide pattern is formed, and a first pattern is formed by processing the lower layer side. Subsequently, on a second DSA condition, a second phase-separated pattern having regularity with respect to the second guide pattern is formed, and a second pattern is formed by processing the lower layer side.
    Type: Grant
    Filed: December 27, 2012
    Date of Patent: July 22, 2014
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Shimon Maeda, Kenji Konomi
  • Publication number: 20140073141
    Abstract: In a method for forming a pattern according to an embodiment, a first guide pattern and a second guide pattern for induced self organization of a DSA material are formed on substrate. On a first DSA condition, a first phase-separated pattern having regularity with respect to the first guide pattern is formed, and a first pattern is formed by processing the lower layer side. Subsequently, on a second DSA condition, a second phase-separated pattern having regularity with respect to the second guide pattern is formed, and a second pattern is formed by processing the lower layer side.
    Type: Application
    Filed: December 27, 2012
    Publication date: March 13, 2014
    Inventors: Shimon MAEDA, Kenji Konomi
  • Publication number: 20130328155
    Abstract: The disclosed aspects relate to controlling density of photomasks. One or more unprintable auxiliary patterns can be placed near a mask feature as well as onto a location of a feature of the main pattern. If a density is measured and is not within an acceptable density range, one or more printable auxiliary patterns can be replaced with unprintable auxiliary patterns and/or one or more unprintable auxiliary patterns can be replaced with printable auxiliary patterns. The disclosed aspects can be utilized to create a photomask and/or a semiconductor device, such as a large scale integrated circuit device, that comprises the photomask.
    Type: Application
    Filed: June 7, 2012
    Publication date: December 12, 2013
    Applicant: TOSHIBA AMERICA ELECTRONIC COMPONENTS, INC.
    Inventor: Kenji Konomi
  • Publication number: 20130073146
    Abstract: A steering system including a steering member provided in a vehicle and configured to be rotated, an adjustment apparatus configured to adjust a rotary direction vibration of the steering member, and a steering control apparatus configured to control the adjustment apparatus, in accordance with an operating condition of the vehicle, so as to adjust the vibration.
    Type: Application
    Filed: May 20, 2011
    Publication date: March 21, 2013
    Applicant: Toyota Jidosha Kabushiki Kaisha
    Inventors: Kenji Konomi, Yuji Ebihara
  • Patent number: 8127256
    Abstract: A pattern data generation method according to an example of the present invention includes based on design pattern data of a circuit including a plurality of MIS transistors having the same gate size, identifying types of the plurality of MIS transistors, setting size specs for gate patterns of the plurality of MIS transistors, the size specs being different for different types of the MIS transistors, and verifying whether gate patterns of the MIS transistors predicted by simulation using mask pattern data for forming the MIS transistors satisfy the size specs.
    Type: Grant
    Filed: October 16, 2008
    Date of Patent: February 28, 2012
    Assignee: Kabushiki Kaisha Toshiba
    Inventor: Kenji Konomi
  • Publication number: 20100234973
    Abstract: A specification of a layout of a layout pattern arranged on a layer is set based on three-dimensional structures of layers of a semiconductor integrated circuit. It is verified whether a layout pattern formed on a wafer based on design layout data subjected to proximity correction satisfies the specification.
    Type: Application
    Filed: February 11, 2010
    Publication date: September 16, 2010
    Inventor: Kenji KONOMI
  • Publication number: 20090190108
    Abstract: A system and method of leveling the topography of a semiconductor wafer surface is presented. The system may induce low-order lens aberration to control the focal plane dynamically. The system may include a leveling sensor which measures the changes in topography on the surface, as well as an analyzer to determine the aberration to be induced. In addition, the system may include a controller that dynamically adjusts at least one lens to induce such aberration. In another arrangement, the system may control the focal plane by dividing the exposure slit into smaller slits. In this arrangement, the analyzer may be used to determine the appropriate number of divisions to make to produce a focal plane that closely matches the surface of the wafer. In addition, the controller may adjust the stage height and tilt for each division to produce such a focal plane.
    Type: Application
    Filed: January 30, 2008
    Publication date: July 30, 2009
    Applicant: TOSHIBA AMERICA ELECTRONIC COMPONENTS, INC.
    Inventors: Tatsuhiko Ema, Kenji Konomi
  • Publication number: 20090119627
    Abstract: A pattern data generation method according to an example of the present invention includes based on design pattern data of a circuit including a plurality of MIS transistors having the same gate size, identifying types of the plurality of MIS transistors, setting size specs for gate patterns of the plurality of MIS transistors, the size specs being different for different types of the MIS transistors, and verifying whether gate patterns of the MIS transistors predicted by simulation using mask pattern data for forming the MIS transistors satisfy the size specs.
    Type: Application
    Filed: October 16, 2008
    Publication date: May 7, 2009
    Inventor: Kenji KONOMI