Patents by Inventor Kenji Kozakai
Kenji Kozakai has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 7283408Abstract: A nonvolatile memory apparatus which need not compare an access address with a faulty address every time for rescuing from any fault is to be provided. The apparatus has memory arrays, data registers for inputting and outputting data to and from the memory arrays, and control circuits. The control circuits, after transferring a plurality of sets of data from the memory arrays to the data registers in response to an instruction to read data, take out rescuing data out of the plurality of sets of data transferred to the data registers, and perform processing to replace with the taken-out rescuing data corresponding faulty addresses on the data register to enable the data on the data register to be supplied to the outside. When any faulty data in the read data are to be replaced with rescuing data on any data register to which data have been transferred from any memory array, read access addresses need not be checked whether or not they are faulty every time an access address is supplied from outside.Type: GrantFiled: June 23, 2005Date of Patent: October 16, 2007Assignee: Renesas Technology Corp.Inventors: Tsutomu Nakajima, Satoshi Noda, Kenji Kozakai, Atsushi Tokairin
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Publication number: 20070206418Abstract: For a nonvolatile memory permitting electrical writing and erasing of information to be stored, such as a flash memory, the load on the system developer is to be reduced, and it is to be made possible to avoid, even if such important data for the system as management and address translation information are damaged, an abnormal state in which the system becomes unable to operate.Type: ApplicationFiled: May 8, 2007Publication date: September 6, 2007Inventors: Kenji Kozakai, Takeshi Nakamura, Tatsuya Ishii, Motoyasu Tsunoda, Shinya Iguchi, Junichi Maruyama
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Patent number: 7230859Abstract: For a nonvolatile memory permitting electrical writing and erasing of information to be stored, such as a flash memory, the load on the system developer is to be reduced, and it is to be made possible to avoid, even if such important data for the system as management and address translation information are damaged, an abnormal state in which the system becomes unable to operate.Type: GrantFiled: January 12, 2006Date of Patent: June 12, 2007Assignee: Renesas Technology Corp.Inventors: Kenji Kozakai, Takeshi Nakamura, Tatsuya Ishii, Motoyasu Tsunoda, Shinya Iguchi, Junichi Maruyama
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Patent number: 7116578Abstract: In a card storage device containing a non-volatile memory and a buffer memory, the buffer memory includes a plurality of banks. Data is transferred sequentially from a host CPU to the banks of the buffer memory, data is transferred to the non-volatile memory from a bank that becomes full, a write operation is started when one unit of data to be written into the non-volatile memory at a time has been transferred and, without waiting for the data to be written, the next write data is transferred from the host CPU to a bank from which write data has been transferred.Type: GrantFiled: March 11, 2004Date of Patent: October 3, 2006Assignees: Renesas Technology Corp., Hitachi ULSI Systems Co., Ltd.Inventors: Motoki Kanamori, Takayuki Tamura, Kenji Kozakai, Atsushi Shikata, Shinsuke Asari
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Publication number: 20060114726Abstract: For a nonvolatile memory permitting electrical writing and erasing of information to be stored, such as a flash memory, the load on the system developer is to be reduced, and it is to be made possible to avoid, even if such important data for the system as management and address translation information are damaged, an abnormal state in which the system becomes unable to operate.Type: ApplicationFiled: January 12, 2006Publication date: June 1, 2006Inventors: Kenji Kozakai, Takeshi Nakamura, Tatsuya Ishii, Motoyasu Tsunoda, Shinya Iguchi, Junichi Maruyama
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Patent number: 7012845Abstract: For a nonvolatile memory permitting electrical writing and erasing of information to be stored, such as a flash memory, the load on the system developer is to be reduced, and it is to be made possible to avoid, even if such important data for the system as management and address translation information are damaged, an abnormal state in which the system becomes unable to operate.Type: GrantFiled: February 9, 2005Date of Patent: March 14, 2006Assignee: Renesas Technology Corp.Inventors: Kenji Kozakai, Takeshi Nakamura, Tatsuya Ishii, Motoyasu Tsunoda, Shinya Iguchi, Junichi Maruyama
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Publication number: 20060039230Abstract: An object of the present invention is to provide a semiconductor memory device capable of preventing a defect caused by falling of a word line and deterioration in patterning precision due to disturbance of the pitch of word lines at an end of a memory block. Plural dummy word lines are disposed at an end of a memory block, a word driver is mounted for the dummy word line to control the threshold voltage of a dummy memory cell formed below the dummy word line. Also at the time of operating a memory area for storing data from the outside, a bias is applied to the dummy word line. The invention can prevent a defect caused by falling of a word line and deterioration in patterning precision due to disturbance of the pitches of word lines at an end of a memory block, and realize high yield and reliably operation.Type: ApplicationFiled: July 14, 2005Publication date: February 23, 2006Inventors: Hideaki Kurata, Yoshihiro Ikeda, Masahiro Shimizu, Kenji Kozakai, Satoshi Noda
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Patent number: 7002853Abstract: A memory card (1) includes an electrically rewritable non-volatile memory (4), a data processor (3) having a function of executing instructions, and managing the allocation of file data in the non-volatile memory, an interface control circuit (2) having a function of establishing an external interface, for controlling the execution of instructions by the data processor in response to external commands and for controlling access to the non-volatile memory and a buffer memory (7) for temporarily storing the file data. The interface control circuit includes command control means for decoding a first command externally supplied and for instructing the data processor to fetch an instruction from the buffer memory and to operate.Type: GrantFiled: June 24, 2004Date of Patent: February 21, 2006Assignee: Renesas Technology Corp.Inventors: Kenji Kozakai, Yuusuke Jono, Motoki Kanamori, Kazunori Furusawa, Atsushi Shikata, Yosuke Yukawa
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Publication number: 20060026489Abstract: To provide a technique which enables a load on a controller to be reduced by rapidly detecting n-bit errors during writing/erasing on a chip in ECC in a nonvolatile memory. A flash memory of the present invention, which is a nonvolatile memory that includes plural electrically erasable and writable nonvolatile memory cells and performs write-and-verify processing in a write operation on the nonvolatile memory cells, includes an ECC determination circuit that counts the number of bits of write error detected in the write-and-verify processing, and outputs the information, and a status register for holding pass/fail information of the write operation and the information about the number of bits of write error outputted from the ECC determination circuit.Type: ApplicationFiled: July 18, 2005Publication date: February 2, 2006Inventors: Satoshi Noda, Kenji Kozakai, Toru Matsushita, Yusuke Jono
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Publication number: 20060023554Abstract: A read command having designated a bank, can be inputted from outside. A read command having designated a bank can be inputted from outside while an operation for reading from a memory array to a data buffer is being performed at the bank. Further, a read command having designated a bank is inputted from outside, and a buffer read command having designated a bank is inputted from outside while an operation for reading from a memory array to a data buffer is being performed at the bank, whereby reading from the data buffer of the bank to the outside is enabled.Type: ApplicationFiled: June 28, 2005Publication date: February 2, 2006Inventors: Toru Matsushita, Kenji Kozakai, Hajime Tanabe, Takashi Horii
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Publication number: 20060002199Abstract: A nonvolatile memory apparatus which need not compare an access address with a faulty address every time for rescuing from any fault is to be provided. The apparatus has memory arrays, data registers for inputting and outputting data to and from the memory arrays, and control circuits. The control circuits, after transferring a plurality of sets of data from the memory arrays to the data registers in response to an instruction to read data, take out rescuing data out of the plurality of sets of data transferred to the data registers, and perform processing to replace with the taken-out rescuing data corresponding faulty addresses on the data register to enable the data on the data register to be supplied to the outside. When any faulty data in the read data are to be replaced with rescuing data on any data register to which data have been transferred from any memory array, read access addresses need not be checked whether or not they are faulty every time an access address is supplied from outside.Type: ApplicationFiled: June 23, 2005Publication date: January 5, 2006Inventors: Tsutomu Nakajima, Satoshi Noda, Kenji Kozakai, Atsushi Tokairin
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Publication number: 20050262292Abstract: A memory card (1) includes an electrically rewritable non-volatile memory (4), a data processor (3) having a function of executing instructions, and managing the allocation of file data in the non-volatile memory, an interface control circuit (2) having a function of establishing an external interface, for controlling the execution of instructions by the data processor in response to external commands and for controlling access to the non-volatile memory and a buffer memory (7) for temporarily storing the file data. The interface control circuit includes command control means for decoding a first command externally supplied and for instructing the data processor to fetch an instruction from the buffer memory and to operate.Type: ApplicationFiled: July 18, 2005Publication date: November 24, 2005Inventors: Kenji Kozakai, Yuusuke Jono, Motoki Kanamori, Kazunori Furusawa, Atsushi Shikata, Yosuke Yukawa
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Publication number: 20050141300Abstract: For a nonvolatile memory permitting electrical writing and erasing of information to be stored, such as a flash memory, the load on the system developer is to be reduced, and it is to be made possible to avoid, even if such important data for the system as management and address translation information are damaged, an abnormal state in which the system becomes unable to operate.Type: ApplicationFiled: February 9, 2005Publication date: June 30, 2005Inventors: Kenji Kozakai, Takeshi Nakamura, Tatsuya Ishii, Motoyasu Tsunoda, Shinya Iguchi, Junichi Maruyama
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Patent number: 6868032Abstract: For a nonvolatile memory permitting electrical writing and erasing of information to be stored, such as a flash memory, the load on the system developer is to be reduced, and it is to be made possible to avoid, even if such important data for the system as management and address translation information are damaged, an abnormal state in which the system becomes unable to operate.Type: GrantFiled: August 10, 2004Date of Patent: March 15, 2005Assignee: Renesas Technology Corp.Inventors: Kenji Kozakai, Takeshi Nakamura, Tatsuya Ishii, Motoyasu Tsunoda, Shinya Iguchi, Junichi Maruyama
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Publication number: 20050007860Abstract: For a nonvolatile memory permitting electrical writing and erasing of information to be stored, such as a flash memory, the load on the system developer is to be reduced, and it is to be made possible to avoid, even if such important data for the system as management and address translation information are damaged, an abnormal state in which the system becomes unable to operate.Type: ApplicationFiled: August 10, 2004Publication date: January 13, 2005Inventors: Kenji Kozakai, Takeshi Nakamura, Tatsuya Ishii, Motoyasu Tsunoda, Shinya Iguchi, Junichi Maruyama
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Publication number: 20040236910Abstract: A memory card (1) includes an electrically rewritable non-volatile memory (4), a data processor (3) having a function of executing instructions, and managing the allocation of file data in the non-volatile memory, an interface control circuit (2) having a function of establishing an external interface, for controlling the execution of instructions by the data processor in response to external commands and for controlling access to the non-volatile memory and a buffer memory (7) for temporarily storing the file data. The interface control circuit includes command control means for decoding a first command externally supplied and for instructing the data processor to fetch an instruction from the buffer memory and to operate.Type: ApplicationFiled: June 24, 2004Publication date: November 25, 2004Applicant: Hitachi, Ltd.Inventors: Kenji Kozakai, Yuusuke Jono, Motoki Kanamori, Kazunori Furusawa, Atsushi Shikata, Yosuke Yukawa
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Publication number: 20040174742Abstract: In a card storage device containing a non-volatile memory and a buffer memory, the buffer memory includes a plurality of banks. Data is transferred sequentially from a host CPU to the banks of the buffer memory, data is transferred to the non-volatile memory from a bank that becomes full, a write operation is started when one unit of data to be written into the non-volatile memory at a time has been transferred and, without waiting for the data to be written, the next write data is transferred from the host CPU to a bank from which write data has been transferred.Type: ApplicationFiled: March 11, 2004Publication date: September 9, 2004Applicants: Renesas Technology Corp., Hitachi ULSI Systems Co., Ltd.Inventors: Motoki Kanamori, Takayuki Tamura, Kenji Kozakai, Atsushi Shikata, Shinsuke Asari
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Patent number: 6788575Abstract: For a nonvolatile memory permitting electrical writing and erasing of information to be stored, such as a flash memory, the load on the system developer is to be reduced, and it is to be made possible to avoid, even if such important data for the system as management and address translation information are damaged, an abnormal state in which the system becomes unable to operate. The nonvolatile memory is provided with a replacing function to replace a group of memory cells including defective memory cells which are incapable of normal writing or erasion with a group of memory cells including no defective memory cell, a numbers of rewrites averaging function to grasp the number of data rewrites in each group of memory cells and to so perform replacement of memory cell groups that there may arise no substantial difference in the number of rewrites among a plurality of memory cell groups, and an error correcting function to detect and correct any error in data stored in the memory array.Type: GrantFiled: September 23, 2003Date of Patent: September 7, 2004Assignee: Renesas Technology Corp.Inventors: Kenji Kozakai, Takeshi Nakamura, Tatsuya Ishii, Motoyasu Tsunoda, Shinya Iguchi, Junichi Maruyama
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Patent number: 6731537Abstract: In a card storage device containing a non-volatile memory and a buffer memory, the buffer memory includes a plurality of banks. Data is transferred sequentially from a host CPU to the banks of the buffer memory, data is transferred to the non-volatile memory from a bank that becomes full, a write operation is started when one unit of data to be written into the non-volatile memory at a time has been transferred and, without waiting for the data to be written, the next write data is transferred from the host CPU to a bank from which write data has been transferred.Type: GrantFiled: February 26, 2002Date of Patent: May 4, 2004Assignees: Renesas Technology Corp., Hitachi ULSI Systems Co., Ltd.Inventors: Motoki Kanamori, Takayuki Tamura, Kenji Kozakai, Atsushi Shikata, Shinsuke Asari
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Publication number: 20040057316Abstract: For a nonvolatile memory permitting electrical writing and erasing of information to be stored, such as a flash memory, the load on the system developer is to be reduced, and it is to be made possible to avoid, even if such important data for the system as management and address translation information are damaged, an abnormal state in which the system becomes unable to operate.Type: ApplicationFiled: September 23, 2003Publication date: March 25, 2004Applicant: Renesas Technology Corp.Inventors: Kenji Kozakai, Takeshi Nakamura, Tatsuya Ishii, Motoyasu Tsunoda, Shinya Iguchi, Junichi Maruyama