Abstract: A method for fabricating packaged semiconductor devices in panel format; placing a panel-sized metallic grid with openings on an adhesive tape (292); attaching semiconductor chips—coated with a polymer layer having windows for chip terminals —face-down onto the tape (293); laminating low CTE insulating material to fill gaps between chips and grid (294); turning over assembly to place carrier under backside of chips and lamination and to remove tape (295); plasma-cleaning assembly front side, sputtering uniform metal layer across assembly (296); optionally plating metal layer (297); and patterning sputtered layer to form rerouting traces and extended contact pads for assembly (298).

Abstract: A method for forming a packaged electronic device including a package substrate having a top substrate surface including a die attach region including at least one land pad thereon and a first dielectric layer positioned lateral to the land pad and a non-die attach region. A second dielectric layer is formed on the top substrate surface of the package substrate. An IC die which is mounted to the top substrate surface of the package substrate. An underfill layer is formed between the IC die and the die attach region.

Abstract: A method for forming a packaged electronic device including a package substrate having a top substrate surface including a die attach region including at least one land pad thereon and a first dielectric layer positioned lateral to the land pad and a non-die attach region. A second dielectric layer is formed on the top substrate surface of the package substrate. An IC die which is mounted to the top substrate surface of the package substrate. An underfill layer is formed between the IC die and the die attach region.

Abstract: A groove is formed in a metal sheet by performing an irradiation engraving operation on a first surface area of the metal sheet. The irradiation engraving operation displaces metal particles from the first surface area onto a second surface area of the metal sheet. The environment of the irradiation engraving operation is controlled to reduce the number of displaced metal particles that would otherwise weld to the second surface area.

Abstract: A packaged electronic device including a package substrate having a top substrate surface including a die attach region including at least one land pad thereon and a first dielectric layer positioned lateral to the land pad and a non-die attach region. The non-die attach region includes a second dielectric layer, wherein a thickness of the second dielectric layer is>a thickness of the first dielectric layer by at least 5 ?m. An IC die has a top semiconductor surface including active circuitry and at least one bonding conductor formed on the top semiconductor surface, and a bottom surface, wherein the bonding conductor of the IC die is joined to the land pad of the package substrate. An underfill layer is between the IC die and the die attach region.

Abstract: A semiconductor device assembly can include a semiconductor chip, a receiving substrate, and a spacer structure interposed between the semiconductor chip and the receiving substrate. The spacer provides an unoccupied space between a pillar and a bond finger for excess conductive material, which can otherwise flow from between the pillar and bond finger and result in a conductive short. The spacer can also provide an offset between the pillar and bond finger.

Abstract: Various embodiments provide semiconductor devices having cavity substrate structures for package-on-package assembly and methods for their fabrication. In one embodiment, the cavity substrate structure can include at least one top interconnect via formed within a top substrate. The top substrate can be disposed over a base substrate having at least one base interconnect via that is not aligned with the top interconnect via. Semiconductor dies can be assembled in an open cavity of the top substrate and attached to a base center portion of the base substrate of the cavity substrate structure. A top semiconductor package can be mounted over the top substrate of the cavity substrate structure.

Abstract: A semiconductor device assembly can include a semiconductor chip, a receiving substrate, and a spacer structure interposed between the semiconductor chip and the receiving substrate. The spacer provides an unoccupied space between a pillar and a bond finger for excess conductive material, which can otherwise flow from between the pillar and bond finger and result in a conductive short. The spacer can also provide an offset between the pillar and bond finger.

Abstract: A packaged electronic device including a package substrate having a top substrate surface including a die attach region including at least one land pad thereon and a first dielectric layer positioned lateral to the land pad and a non-die attach region. The non-die attach region includes a second dielectric layer, wherein a thickness of the second dielectric layer is>a thickness of the first dielectric layer by at least 5 ?m. An IC die has a top semiconductor surface including active circuitry and at least one bonding conductor formed on the top semiconductor surface, and a bottom surface, wherein the bonding conductor of the IC die is joined to the land pad of the package substrate. An underfill layer is between the IC die and the die attach region.

Abstract: An integrated circuit (IC) and a method of forming the device are provided. The device includes a substrate and a metal trace formed on the substrate, the metal trace including a bond area and a routing area. The routing area includes a rough surface for promoting adhesion to underfill of a flip-chip die. The flip-chip die can include a bump bond connected to the bond area of the metal trace. The underfill is between the substrate and an active surface of the flip-chip die, the rough surface of the routing area adhering to the underfill in the absence of a photo resist on the routing area of the metal trace.

Abstract: In one aspect, the invention provides a semiconductor device that comprises a semiconductor device packaging substrate core. A first interconnect structure is located within a mold region and on a die side of the substrate core and has a first conductive metal density associated therewith. A second interconnect structure is located within the mold region and on a solder joint side of the substrate core and has a second conductive metal density associated therewith, wherein the second conductive metal density within the mold region is about equal to or less than the first conductive metal density within the mold region.

Abstract: A method of forming an electronic assembly including a plurality of IC die having bonding terminals that have a solderable material thereon and a workpiece. The workpiece includes workpiece contact pads including an elevated ring having a ring height at least 5 ?m above a minimum contact pad height in an indented bonding region that is within the elevated ring. The bonding terminals and/or the plurality of workpiece contact pads include solder thereon. A plurality of IC die are mounted on the workpiece. Heat is applied so that the solder becomes tacky while remaining below its melting temperature to obtain a tacked position. The plurality of IC die are pressed using a pressing tool to heat the solder to a peak temperature that is above the melting temperature. The elevated ring resists horizontal movement of the plurality of IC die from their tacked positions during pressing.

Abstract: Methods for assembling multilayer semiconductor device packages are disclosed. A base substrate having device mounting sites is provided. A number of semiconductor devices are connected to the device mounting sites. Upper boards are attached to the base substrate and over each of the coupled devices. The method includes steps of testing one or more of the base substrate, semiconductor device, or upper board, prior to operably connecting one to another.

Abstract: A semiconductor device 39. The device includes an interposer 31 having two major surfaces. The first surface 311 includes patterned metal conductors and bond pads 351, and the second surface includes an array of solder balls 33. The device includes a semiconductor chip 30 having a top surface and a back surface, the back surface of the chip adjacent the interposer 31, and the top surface including a plurality of terminals. Also included is a layer of polymeric material 34 disposed on the first surface 311 of the interposer covering the area of the interposer over the solder ball array. At least a portion of the polymeric layer is between the chip 30 and the interposer 31. The device further includes a plurality of electrical connections 35 between the chip terminals and the bond pads 351 on the interposer.

Abstract: In one aspect, the invention provides a semiconductor device that comprises a semiconductor device packaging substrate core. A first interconnect structure is located within a mold region and on a die side of the substrate core and has a first conductive metal density associated therewith. A second interconnect structure is located within the mold region and on a solder joint side of the substrate core and has a second conductive metal density associated therewith, wherein the second conductive metal density within the mold region is about equal to or less than the first conductive metal density within the mold region.

Abstract: An insulating layer (3) having an opening portion (3a) at a position conformable to an electrode pad (2) is formed. Next, a resin projection portion (4) is formed on the insulating layer (3). Thereafter, a resist film is formed which has opening portions made in regions conformable to the opening portion (3a), the resin projection portion (4) and the region sandwiched therebetween. A Cu plating layer (6) is formed by electrolytic copper plating, using the resist film as a mask.

Abstract: A semiconductor device 39. The device includes an interposer 31 having two major surfaces. The first surface 311 includes patterned metal conductors and bond pads 351, and the second surface includes an array of solder balls 33. The device includes a semiconductor chip 30 having a top surface and a back surface, the back surface of the chip adjacent the interposer 31, and the top surface including a plurality of terminals. Also included is a layer of polymeric material 34 disposed on the first surface 311 of the interposer covering the area of the interposer over the solder ball array. At least a portion of the polymeric layer is between the chip 30 and the interposer 31. The device further includes a plurality of electrical connections 35 between the chip terminals and the bond pads 351 on the interposer.

Abstract: An insulating layer (3) having an opening portion (3a) at a position conformable to an electrode pad (2) is formed. Next, a resin projection portion (4) is formed on the insulating layer (3). Thereafter, a resist film is formed which has opening portions made in regions conformable to the opening portion (3a), the resin projection portion (4) and the region sandwiched therebetween. A Cu plating layer (6) is formed by electrolytic copper plating, using the resist film as a mask.

Abstract: An apparatus comprising an integrated circuit structure is provided. The integrated circuit structure comprises a substrate and a photoreceiver. The substrate has a first side and a second side opposite the first side and includes a first light passage area operable to allow light to pass through. The photoreceiver has an aperture located on a first side of the photoreceiver and is flip-chip mounted to the substrate such that the first side of the photoreceiver faces the second side of the substrate. The photoreceiver is operable to translate light signals received through the aperture into digital signals and to transmit the digital signals. The first light passage area is aligned with the aperture of the photoreceiver such that the light signals may be received through the light passage area and into the aperture of the photoreceiver.

Abstract: A semiconductor device 39. The device includes an interposer 31 having two major surfaces. The first surface 311 includes patterned metal conductors and bond pads 351, and the second surface includes an array of solder balls 33. The device includes a semiconductor chip 30 having a top surface and a back surface, the back surface of the chip adjacent the interposer 31, and the top surface including a plurality of terminals. Also included is a layer of polymeric material 34 disposed on the first surface 311 of the interposer covering the area of the interposer over the solder ball array. At least a portion of the polymeric material layer is between the chip 30 and the interposer 31. The device further includes a plurality of electrical connections 35 between the chip terminals and the bond pads 351 on the interposer.