Patents by Inventor Kenji Nanba

Kenji Nanba has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 11871682
    Abstract: A quantum device (100) includes: an interposer (112); a quantum chip (111); a first connection part (130) that is provided between the interposer (112) and the quantum chip (111) and electrically connects a wiring layer of the interposer (112) to a wiring layer of the quantum chip (111); and a second connection part (140) that is provided on a main surface of the interposer (112) where the first connection part (130) is arranged and is connected to a cooling plate (115).
    Type: Grant
    Filed: June 16, 2021
    Date of Patent: January 9, 2024
    Assignee: NEC CORPORATION
    Inventors: Kenji Nanba, Ayami Yamaguchi, Akira Miyata, Katsumi Kikuchi, Suguru Watanabe, Takanori Nishi, Hideyuki Satou
  • Patent number: 11805708
    Abstract: A quantum device according to an example embodiment includes a quantum chip 10, and an interposer 20 on which the quantum chip 10 is mounted, in which the interposer 20 includes a conductive wiring line CL1 electrically connected to the quantum chip 10, a mounting surface 21 of the interposer 20 on which the quantum chip 10 is mounted or an opposite surface 22 opposite to the mounting surface 21 includes a first area AR11 and a second area AR12 different from the first area AR11 as viewed in a direction perpendicular to the mounting surface 21 or the opposite surface 22, the conductive wiring line CL1 is disposed in the first area AR11 on the mounting surface 21 or the opposite surface 22, and a movable member 60 is in contact with the second area AR12 of the interposer 20.
    Type: Grant
    Filed: June 15, 2021
    Date of Patent: October 31, 2023
    Assignee: NEC CORPORATION
    Inventors: Katsumi Kikuchi, Akira Miyata, Suguru Watanabe, Takanori Nishi, Hideyuki Satou, Kenji Nanba, Ayami Yamaguchi
  • Publication number: 20230345844
    Abstract: Provided is a quantum device capable of improving cooling performance. A quantum device includes a quantum chip configured to perform information processing using a quantum state, and an interposer on which the quantum chip is mounted, and the quantum chip is arranged inside a recess 31 formed in a sample stage having a cooling function, and a part of the interposer is in contact with the sample stage. The quantum chip may have a first surface mounted on the interposer and a second surface opposite to the first surface, and at least a part of the second surface may be in contact with an inner surface of the recess.
    Type: Application
    Filed: June 5, 2020
    Publication date: October 26, 2023
    Applicant: NEC Corporation
    Inventors: Katsumi KIKUCHI, Akira MIYATA, Suguru WATANABE, Takanori NISHI, Hideyuki SATOU, Kenji NANBA, Ayami YAMAGUCHI
  • Patent number: 11798895
    Abstract: A quantum device (100) includes an interposer (112), a quantum chip (111) mounted on the interposer (112), and a shield part (150) provided so as to surround a quantum circuit region of the interposer (112) and the quantum chip (111). Accordingly, the quantum device (100) is able to prevent interference in the quantum circuit region due to exogenous noise.
    Type: Grant
    Filed: June 24, 2021
    Date of Patent: October 24, 2023
    Assignee: NEC CORPORATION
    Inventors: Kenji Nanba, Ayami Yamaguchi, Akira Miyata, Katsumi Kikuchi, Suguru Watanabe, Takanori Nishi, Hideyuki Satou
  • Publication number: 20230309419
    Abstract: A quantum device includes a chip including a superconducting circuit, a first wiring substrate, a second wiring substrate, first connection portions connecting the chip and a wiring layer on a first surface of the first wiring substrate and second connection portions connecting the second wiring substrate and a wiring layer on a second surface of the first wiring substrate, wherein one or more second connection portions arranged in a first row as viewed from the edge of the first substrate are provided at positions corresponding respectively to one or more of the first connection portions arranged in a first row as viewed from the edge and are arranged closer to the edge than the first connection portions arranged in the first row.
    Type: Application
    Filed: March 17, 2023
    Publication date: September 28, 2023
    Applicant: NEC Corporation
    Inventors: Katsumi KIKUCHI, Akira Miyata, Takanori Nishi, Kenji Nanba, Ayami Yamaguchi
  • Patent number: 11696517
    Abstract: A quantum device (100) includes: an interposer (112); a quantum chip (111); and a connection part (130) that is provided between the interposer (112) and the quantum chip (111) and electrically connects a wiring layer of the interposer (112) to a wiring layer of the quantum chip (111), in which the connection part (130) includes: a plurality of pillars (131) arranged on a main surface of the interposer (112); and a metal film (132) provided on a surface of the plurality of pillars (131) in such a way that it contacts the wiring layer of the quantum chip (111) and the thickness of the metal film at outer peripheral parts of the tip of each of the plurality of pillars (131) becomes larger than the thickness of the metal film at a center part of the tip of each of the plurality of pillars (131).
    Type: Grant
    Filed: June 16, 2021
    Date of Patent: July 4, 2023
    Assignee: NEC CORPORATION
    Inventors: Kenji Nanba, Ayami Yamaguchi, Akira Miyata, Katsumi Kikuchi, Suguru Watanabe, Takanori Nishi, Hideyuki Satou
  • Publication number: 20220344562
    Abstract: A quantum device according to an example embodiment includes: a quantum chip with a first surface and a second surface located on a side opposite to the first surface, in the quantum chip, at least a part of a qubit circuit being provided on the second surface; a first interposer with a third surface and a fourth surface located on a side opposite to the third surface, the first interposer being connected to the quantum chip in such a manner that the second surface of the quantum chip is opposed to the third surface of the first interposer; and a second interposer with a fifth surface and a sixth surface located on a side opposite to the fifth surface, the second interposer being connected to the first interposer in such a manner that the fourth surface of the first interpose is opposed to the fifth surface of the second interposer.
    Type: Application
    Filed: April 4, 2022
    Publication date: October 27, 2022
    Applicant: NEC Corporation
    Inventors: Katsumi KIKUCHI, Akira MIYATA, Takanori NISHI, Kenji NANBA, Ayami YAMAGUCHI
  • Publication number: 20210407928
    Abstract: A quantum device (100) includes an interposer (112), a quantum chip (111) mounted on the interposer (112), and a shield part (150) provided so as to surround a quantum circuit region of the interposer (112) and the quantum chip (111). Accordingly, the quantum device (100) is able to prevent interference in the quantum circuit region due to exogenous noise.
    Type: Application
    Filed: June 24, 2021
    Publication date: December 30, 2021
    Applicant: NEC Corporation
    Inventors: Kenji NANBA, Ayami YAMAGUCHI, Akira MIYATA, Katsumi KIKUCHI, Suguru WATANABE, Takanori NISHI, Hideyuki SATOU
  • Publication number: 20210408354
    Abstract: To provide a quantum device capable of preventing a connection member connecting a quantum chip with an interposer from being broken. The quantum device 1 includes at least one quantum chip 10, at least one interposer 20 on which the at least one quantum chip 10 is mounted, and a plurality of connection members 30 formed of a conductor. The plurality of connection members 30 are disposed between the quantum chip 10 and the interposer 20, and connect the quantum chip 10 with the interposer 20. The size of the connection member 30 on the surface along the mounting surface 20s of the interposer 20 is changed according to the position thereof relative to the quantum chip 10.
    Type: Application
    Filed: June 24, 2021
    Publication date: December 30, 2021
    Applicant: NEC Corporation
    Inventors: Katsumi KIKUCHI, Akira MIYATA, Suguru WATANABE, Takanori NISHI, Hideyuki SATOU, Kenji NANBA, Ayami YAMAGUCHI
  • Publication number: 20210408358
    Abstract: A quantum device (100) includes: an interposer (112); a quantum chip (111); a first connection part (130) that is provided between the interposer (112) and the quantum chip (111) and electrically connects a wiring layer of the interposer (112) to a wiring layer of the quantum chip (111); a predetermined signal line (w1) arranged in the wiring layer of the quantum chip (111); first shield wires (ws1) arranged in the wiring layer of the quantum chip (111) along the predetermined signal line (w1); a second shield wire (ws2) arranged in the wiring layer of the interposer (112); and a second connection part (150) that is provided between the interposer (112) and the quantum chip (111) so as to contact the first shield wires (ws1) and the second shield wire (ws2).
    Type: Application
    Filed: June 23, 2021
    Publication date: December 30, 2021
    Applicant: NEC Corporation
    Inventors: Kenji Nanba, Ayami Yamaguchi, Akira Miyata, Katsumi Kikuchi, Suguru Watanabe, Takanori Nishi, Hideyuki Satou
  • Publication number: 20210398893
    Abstract: A quantum device capable of improving a cooling effect while securing the number of terminals is provided. A quantum device according to an example embodiment includes a quantum chip 10, and an interposer 20 on which the quantum chip 10 is mounted, in which the interposer 20 includes a conductive wiring line CL1 electrically connected to the quantum chip 10, and a metal film 70 disposed in a part of the interposer 20 that is in contact with a sample stage 30 having a cooling function, and a mounting surface 21 of the interposer 20 on which the quantum chip 10 is mounted or an opposite surface 22 opposite to the mounting surface 21 includes a first area AR11 and a second area AR12 different from the first area AR11 as viewed in a direction perpendicular to the mounting surface 21 or the opposite surface 22.
    Type: Application
    Filed: June 11, 2021
    Publication date: December 23, 2021
    Applicant: NEC Corporation
    Inventors: Katsumi KIKUCHI, Akira MIYATA, Suguru WATANABE, Takanori NISHI, Hideyuki SATOU, Kenji NANBA, Ayami YAMAGUCHI
  • Publication number: 20210399195
    Abstract: A quantum device capable of effectively cooling a quantum chip and an area (e.g., a space) therearound is provided. A quantum device 1 includes a quantum chip 10 and an interposer 20 on which the quantum chip 10 is located. The interposer 20 includes an interposer substrate 22 and an interposer wiring layer 30. The interposer wiring layer 30 is disposed on a surface 22a of the interposer substrate 22 on a side on which the quantum chip 10 is located. The interposer wiring layer 30 includes, in at least a part thereof, a superconducting material layer 32 formed of a superconducting material and a non-superconducting material layer 34 formed of a non-superconducting material.
    Type: Application
    Filed: June 9, 2021
    Publication date: December 23, 2021
    Applicant: NEC Corporation
    Inventors: Katsumi KIKUCHI, Akira MIYATA, Suguru WATANABE, Takanori NISHI, Hideyuki SATOU, Kenji NANBA, Ayami YAMAGUCHI
  • Publication number: 20210399196
    Abstract: A quantum device capable of securing terminals for external connection is provided. A quantum device according to an example embodiment includes a quantum chip 10, an interposer 20 on which the quantum chip 10 is mounted, and a socket 40 disposed so as to be opposed to the interposer 20, the socket 40 comprising a movable pin 47 and a housing 45 supporting the movable pin 47, in which at least one end of the movable pin 47, which includes the one end and the other end opposite to the one end, is movable relative to the housing 45, the one end being in electrical contact with a terminal of the interposer 20, and the other end is in an electrical contact with a terminal of a board 50 on which a connector 51 is formed, the connector 51 being configured to serve as an external input/output.
    Type: Application
    Filed: June 15, 2021
    Publication date: December 23, 2021
    Applicant: NEC Corporation
    Inventors: Katsumi KIKUCHI, Akira MIYATA, Suguru WATANABE, Takanori NISHI, Hideyuki SATOU, Kenji NANBA, Ayami YAMAGUCHI
  • Publication number: 20210399193
    Abstract: A quantum device (100) includes: an interposer (112); a quantum chip (111); a first connection part (130) that is provided between the interposer (112) and the quantum chip (111) and electrically connects a wiring layer of the interposer (112) to a wiring layer of the quantum chip (111); and a second connection part (140) that is provided on a main surface of the interposer (112) where the first connection part (130) is arranged and is connected to a cooling plate (115).
    Type: Application
    Filed: June 16, 2021
    Publication date: December 23, 2021
    Applicant: NEC Corporation
    Inventors: Kenji NANBA, Ayami YAMAGUCHI, Akira MIYATA, Katsumi KIKUCHI, Suguru WATANABE, Takanori NISHI, Hideyuki SATOU
  • Publication number: 20210399197
    Abstract: A quantum device according to an example embodiment includes a quantum chip 10, and an interposer 20 on which the quantum chip 10 is mounted, in which the interposer 20 includes a conductive wiring line CL1 electrically connected to the quantum chip 10, a mounting surface 21 of the interposer 20 on which the quantum chip 10 is mounted or an opposite surface 22 opposite to the mounting surface 21 includes a first area AR11 and a second area AR12 different from the first area AR11 as viewed in a direction perpendicular to the mounting surface 21 or the opposite surface 22, the conductive wiring line CL1 is disposed in the first area AR11 on the mounting surface 21 or the opposite surface 22, and a movable member 60 is in contact with the second area AR12 of the interposer 20.
    Type: Application
    Filed: June 15, 2021
    Publication date: December 23, 2021
    Applicant: NEC Corporation
    Inventors: Katsumi KIKUCHI, Akira MIYATA, Suguru WATANABE, Takanori NISHI, Hideyuki SATOU, Kenji NANBA, Ayami YAMAGUCHI
  • Publication number: 20210399194
    Abstract: A quantum device (100) includes: an interposer (112); a quantum chip (111); and a connection part (130) that is provided between the interposer (112) and the quantum chip (111) and electrically connects a wiring layer of the interposer (112) to a wiring layer of the quantum chip (111), in which the connection part (130) includes: a plurality of pillars (131) arranged on a main surface of the interposer (112); and a metal film (132) provided on a surface of the plurality of pillars (131) in such a way that it contacts the wiring layer of the quantum chip (111) and the thickness of the metal film at outer peripheral parts of the tip of each of the plurality of pillars (131) becomes larger than the thickness of the metal film at a center part of the tip of each of the plurality of pillars (131).
    Type: Application
    Filed: June 16, 2021
    Publication date: December 23, 2021
    Applicant: NEC Corporation
    Inventors: Kenji NANBA, Ayami YAMAGUCHI, Akira MIYATA, Katsumi KIKUCHI, Suguru WATANABE, Takanori NISHI, Hideyuki SATOU
  • Patent number: 8610269
    Abstract: [Problem] A semiconductor device which achieves a fine pitch, a high throughput and a high connection reliability, especially in flip-chip mounting is provided. A method for manufacturing the semiconductor device and a circuit device using the semiconductor device are also provided. [Means for solving the problem] The semiconductor device has: an electrode; an insulating part having an opening on the electrode; a protruding part formed on the electrode; a protecting part which is formed at the periphery of the protruding part and electrically isolates the protruding part; and a bonding part which is formed on the protecting part by being spaced apart from the protruding part. An upper surface of the protruding part, an upper surface of the protecting part, and an upper surface of the bonding part form the same plane.
    Type: Grant
    Filed: June 23, 2010
    Date of Patent: December 17, 2013
    Assignee: NEC Corporation
    Inventor: Kenji Nanba
  • Publication number: 20120104602
    Abstract: [Problem] A semiconductor device which achieves a fine pitch, a high throughput and a high connection reliability, especially in flip-chip mounting is provided. A method for manufacturing the semiconductor device and a circuit device using the semiconductor device are also provided. [Means for solving the problem] The semiconductor device has: an electrode; an insulating part having an opening on the electrode; a protruding part formed on the electrode; a protecting part which is formed at the periphery of the protruding part and electrically isolates the protruding part; and a bonding part which is formed on the protecting part by being spaced apart from the protruding part. An upper surface of the protruding part, an upper surface of the protecting part, and an upper surface of the bonding part form the same plane.
    Type: Application
    Filed: June 23, 2010
    Publication date: May 3, 2012
    Inventor: Kenji Nanba
  • Publication number: 20090219797
    Abstract: Pulses that are generated from multiple analog input signals are sampled, and signal elements contained in the analog signals are extracted accurately using the said sampling pulses. Binarization circuits where analog input signals A, B, C, and D are converted into pulse signals; a logic operation circuit that generates a sampling pulse upon receiving the input of the 4 pulse signals; and a sample-and-hold circuit samples and holds an input RF signal based on the sampling pulse in order to extract accurately signal elements contained in said RF signal by means of sampling of the RF signal.
    Type: Application
    Filed: May 8, 2008
    Publication date: September 3, 2009
    Applicant: TEXAS INSTRUMENTS INCORPORATED
    Inventors: Masayuki Tahara, Kenji Nanba, Tetsuya Nishiyama
  • Publication number: 20030210956
    Abstract: A method for purifying a layer of contaminated soil is provided, including the following steps: (a) preparing an injection well for injecting a fluid which has a purification capability utilizing one of physical action, chemical reaction, metabolism of microbes and promotion thereof and highly pressurized washing into the layer and (b) injecting the fluid under a high pressure at which one of the physical action, chemical reaction, metabolism of microbes and promotion thereof and highly pressurized washing can be controlled, through injection nozzles provided on a first wall or a first bottom of the injection well. The method has features that the injected fluid stirs and washes the layer to separate or decompose contaminants and the contaminants are eliminated by collecting the fluid containing an undecomposed portion of the contaminants in the layer through a plurality of collection wells.
    Type: Application
    Filed: January 7, 2003
    Publication date: November 13, 2003
    Applicant: TANAKA KANKYO-KAIHATSU CO.
    Inventors: Takeshi Tanaka, Hisashi Nirei, Kenji Nanba, Mio Takeuchi, Asuka Takahashi, Masato Owaki