Patents by Inventor Kenji Sakata

Kenji Sakata has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20220013508
    Abstract: Reliability of a semiconductor device is improved. The semiconductor device PKG1 includes a wiring substrate SUB1, a semiconductor chip CHP1 and a capacitor CDC mounted on the upper surface 2t of the wiring substrate SUB1, and a lid LD formed of a metallic plate covering the semiconductor chip CHP1 and the wiring substrate SUB1. The semiconductor chip CHP1 is bonded to the lid LD via a conductive adhesive layer, and the capacitor CDC, which is thicker than the thickness of the semiconductor chip CHP1, is disposed in the cut off portion 4d1 provided in the lid LD, and is exposed from the lid LD.
    Type: Application
    Filed: September 27, 2021
    Publication date: January 13, 2022
    Inventors: Toshihiko AKIBA, Kenji SAKATA, Nobuhiro KINOSHITA, Yosuke KATSURA
  • Patent number: 11158617
    Abstract: Reliability of a semiconductor device is improved. The semiconductor device PKG1 includes a wiring substrate SUB1, a semiconductor chip CHP1 and a capacitor CDC mounted on the upper surface 2t of the wiring substrate SUB1, and a lid LD formed of a metallic plate covering the semiconductor chip CHP1 and the wiring substrate SUB1. The semiconductor chip CHP1 is bonded to the lid LD via a conductive adhesive layer, and the capacitor CDC, which is thicker than the thickness of the semiconductor chip CHP1, is disposed in the cut off portion 4d1 provided in the lid LD, and is exposed from the lid LD.
    Type: Grant
    Filed: June 18, 2019
    Date of Patent: October 26, 2021
    Assignee: RENESAS ELECTRONICS CORPORATION
    Inventors: Toshihiko Akiba, Kenji Sakata, Nobuhiro Kinoshita, Yosuke Katsura
  • Publication number: 20210320579
    Abstract: An electric motor and a method for manufacturing an electric motor capable of improving rotation balance of an armature and realizing effective brake braking with a simple configuration are provided. In an electric motor including an armature core having a plurality of teeth and teeth within a yoke, a winding wound between the slots, and a commutator having and a plurality of segments to which the winding is connected, the winding has a main winding that applies a rotational force to the armature core and a brake winding that applies a braking force to the armature core, and an H bridge circuit is built between the winding and a power supply, and the main winding and the brake winding of the winding are disposed at positions for adjusting balance when the armature core rotates.
    Type: Application
    Filed: April 6, 2021
    Publication date: October 14, 2021
    Applicant: MITSUBA Corporation
    Inventors: KENJI SAKATA, AKIHIRO KAIHATSU
  • Patent number: 11063009
    Abstract: There is a need to improve reliability of the semiconductor device. A semiconductor device includes a printed circuit board and a semiconductor chip mounted over the printed circuit board. The semiconductor chip includes a pad, an insulation film including an opening to expose part of the pad, and a pillar electrode formed over the pad exposed from the opening. The printed circuit board includes a terminal and a resist layer including an opening to expose part of the terminal. The pillar electrode of the semiconductor chip and the terminal of the printed circuit board are coupled via a solder layer. Thickness h1 of the pillar electrode is measured from the upper surface of the insulation film. Thickness h2 of the solder layer is measured from the upper surface of the resist layer. Thickness h1 is greater than or equal to a half of thickness h2 and is smaller than or equal to thickness h2.
    Type: Grant
    Filed: February 5, 2018
    Date of Patent: July 13, 2021
    Assignee: Renesas Electronics Corporation
    Inventors: Kenji Sakata, Toshihiko Akiba, Takuo Funaya, Hideaki Tsuchiya, Yuichi Yoshida
  • Patent number: 10890243
    Abstract: The motor with deceleration mechanism includes: a motor shaft (11), which is accommodated in a motor case (21) and in which an axial end portion (11a) is formed into a spherical shape; a worm, arranged on the motor shaft (11); a worm wheel, accommodated in a gear frame and engaging with the worm; a radial bearing (41), rotatably supporting the motor shaft (11); and a first thrust bearing (42), which is disposed inside the motor case (21), and in which a shaft facing surface (42s) facing the axial end portion (11a) of the motor shaft (11) and a counter shaft facing surface (42c) on the opposite side are respectively formed spherically; an average sliding radius between the first thrust bearing (42) and the motor case (21) is larger than an average sliding radius between the first thrust bearing (42) and the motor shaft (11).
    Type: Grant
    Filed: April 19, 2019
    Date of Patent: January 12, 2021
    Assignee: MITSUBA Corporation
    Inventors: Kenji Sakata, Hiroyuki Yoshida, Satoru Yoshida
  • Publication number: 20200006303
    Abstract: Reliability of a semiconductor device is improved. The semiconductor device PKG1 includes a wiring substrate SUB1, a semiconductor chip CHP1 and a capacitor CDC mounted on the upper surface 2t of the wiring substrate SUB1, and a lid LD formed of a metallic plate covering the semiconductor chip CHP1 and the wiring substrate SUB1. The semiconductor chip CHP1 is bonded to the lid LD via a conductive adhesive layer, and the capacitor CDC, which is thicker than the thickness of the semiconductor chip CHP1, is disposed in the cut off portion 4d1 provided in the lid LD, and is exposed from the lid LD.
    Type: Application
    Filed: June 18, 2019
    Publication date: January 2, 2020
    Inventors: Toshihiko AKIBA, Kenji SAKATA, Nobuhiro KINOSHITA, Yosuke KATSURA
  • Publication number: 20190331208
    Abstract: The motor with deceleration mechanism includes: a motor shaft (11), which is accommodated in a motor case (21) and in which an axial end portion (11a) is formed into a spherical shape; a worm, arranged on the motor shaft (11); a worm wheel, accommodated in a gear frame and engaging with the worm; a radial bearing (41), rotatably supporting the motor shaft (11); and a first thrust bearing (42), which is disposed inside the motor case (21), and in which a shaft facing surface (42s) facing the axial end portion (11a) of the motor shaft (11) and a counter shaft facing surface (42c) on the opposite side are respectively formed spherically; an average sliding radius between the first thrust bearing (42) and the motor case (21) is larger than an average sliding radius between the first thrust bearing (42) and the motor shaft (11).
    Type: Application
    Filed: April 19, 2019
    Publication date: October 31, 2019
    Applicant: MITSUBA Corporation
    Inventors: KENJI SAKATA, HIROYUKI YOSHIDA, SATORU YOSHIDA
  • Patent number: 10312199
    Abstract: A manufacturing method of a semiconductor device includes preparing a wiring substrate including a first surface, a plurality of first terminals formed on the first surface, and a second surface opposite to the first surface, arranging a first adhesive on the first surface of the wiring substrate, and after the arranging of the first adhesive, mounting a first semiconductor chip, which includes a first front surface, a plurality of first front electrodes formed on the first front surface, a first rear surface opposite to the first front surface, a plurality of first rear electrodes formed on the first rear surface, and a plurality of through electrodes electrically connecting the plurality of first front electrodes to the plurality of first rear electrodes, on the first surface of the wiring substrate via the first adhesive.
    Type: Grant
    Filed: March 30, 2018
    Date of Patent: June 4, 2019
    Assignee: RENESAS ELECTRONICS CORPORATION
    Inventors: Shinji Watanabe, Tsuyoshi Kida, Yoshihiro Ono, Kentaro Mori, Kenji Sakata, Yusuke Yamada
  • Patent number: 10229392
    Abstract: A group supporting apparatus and related computer readable recording medium to execute a process including: collecting input contents, which are input by participants via terminals, from the terminals; arranging the collected input contents into input content groups based on groups to which the participants belong; setting a representative flag on each of representative input contents selected from the respective input content groups; extracting the representative input contents and matching input contents, which match a predetermined extracting condition and are different from the representative input contents, from the collected input contents; and displaying a list of the representative input contents and the matching input contents on a display device that all the participants are able to view at a same time.
    Type: Grant
    Filed: August 10, 2016
    Date of Patent: March 12, 2019
    Assignee: FUJITSU LIMITED
    Inventors: Hidehiko Mayumi, Toshio Tanaka, Takeaki Kobayashi, Takehiro Nabae, Kenji Sakata
  • Patent number: 10141273
    Abstract: In a semiconductor device according to an embodiment, a second semiconductor chip is mounted on a first rear surface of a first semiconductor chip. Also, the first rear surface of the first semiconductor chip includes a first region in which a plurality of first rear electrodes electrically connected to the second semiconductor chip via a protrusion electrode are formed and a second region which is located on a peripheral side relative to the first region and in which a first metal pattern is formed. In addition, a protrusion height of the first metal pattern with respect to the first rear surface is smaller than a protrusion height of each of the plurality of first rear electrodes with respect to the first rear surface.
    Type: Grant
    Filed: April 14, 2014
    Date of Patent: November 27, 2018
    Assignee: RENESAS ELECTRONICS CORPORATION
    Inventors: Shinji Watanabe, Tsuyoshi Kida, Yoshihiro Ono, Kentaro Mori, Kenji Sakata, Yusuke Yamada
  • Publication number: 20180294239
    Abstract: There is a need to improve reliability of the semiconductor device. A semiconductor device includes a printed circuit board and a semiconductor chip mounted over the printed circuit board. The semiconductor chip includes a pad, an insulation film including an opening to expose part of the pad, and a pillar electrode formed over the pad exposed from the opening. The printed circuit board includes a terminal and a resist layer including an opening to expose part of the terminal. The pillar electrode of the semiconductor chip and the terminal of the printed circuit board are coupled via a solder layer. Thickness h1 of the pillar electrode is measured from the upper surface of the insulation film. Thickness h2 of the solder layer is measured from the upper surface of the resist layer. Thickness h1 is greater than or equal to a half of thickness h2 and is smaller than or equal to thickness h2.
    Type: Application
    Filed: February 5, 2018
    Publication date: October 11, 2018
    Inventors: Kenji SAKATA, Toshihiko AKIBA, Takuo FUNAYA, Hideaki TSUCHIYA, Yuichi YOSHIDA
  • Publication number: 20180226362
    Abstract: A manufacturing method of a semiconductor device includes preparing a wiring substrate including a first surface, a plurality of first terminals formed on the first surface, and a second surface opposite to the first surface, arranging a first adhesive on the first surface of the wiring substrate, and after the arranging of the first adhesive, mounting a first semiconductor chip, which includes a first front surface, a plurality of first front electrodes formed on the first front surface, a first rear surface opposite to the first front surface, a plurality of first rear electrodes formed on the first rear surface, and a plurality of through electrodes electrically connecting the plurality of first front electrodes to the plurality of first rear electrodes, on the first surface of the wiring substrate via the first adhesive.
    Type: Application
    Filed: March 30, 2018
    Publication date: August 9, 2018
    Inventors: Shinji Watanabe, Tsuyoshi Kida, Yoshihiro Ono, Kentaro Mori, Kenji Sakata, Yusuke Yamada
  • Patent number: 9905529
    Abstract: A method for manufacturing a semiconductor device includes the steps of mounting a Si interposer over a printed wiring substrate, plasma-cleaning an upper surface of the Si interposer, disposing an NCF over the upper surface of the Si interposer, and mounting a semiconductor chip over the upper surface of the Si interposer through the NCF. Also, the method includes the step of electrically coupling each of plural electrodes of a second substrate and each of plural electrode pads of the semiconductor chip with each other through plural bump electrodes by reflow, and the surface of the Si interposer is plasma-cleaned before attaching the NCF to the Si interposer.
    Type: Grant
    Filed: March 2, 2016
    Date of Patent: February 27, 2018
    Assignee: RENESAS ELECTRONICS CORPORATION
    Inventors: Kenji Sakata, Tsuyoshi Kida, Yoshihiro Ono
  • Patent number: 9761149
    Abstract: A presenter selection support apparatus including: a display unit configured to display one or more opinions input from each of a plurality of terminals; a selection unit configured to select any one of opinions that belongs to a certain group based on a predetermined criterion when the certain group among at least one group formed by being classified from opinions displayed in the display unit is designated; and an instruction unit configured to instruct a terminal, in which an opinion other than the selected opinion is input, to display a screen in which each of a plurality of items related to relevancy to the selected opinion is selectable, wherein the predetermined criterion is a criterion used to specify any one terminal based on the number of times that one item among the plurality of items is selected in the past in each of the plurality of terminals.
    Type: Grant
    Filed: May 5, 2014
    Date of Patent: September 12, 2017
    Assignee: FUJITSU LIMITED
    Inventors: Hidehiko Mayumi, toshio tanaka, Takeaki Kobayashi, Kenji Sakata
  • Publication number: 20170242955
    Abstract: A method includes: a first step of designing the semiconductor device by using CAD and outputting design CAD data; a second step of correcting the design CAD data to correspond to a matching trial object of the semiconductor device and outputting corrected CAD data; a third step of manufacturing the semiconductor device based on the design CAD data; a fourth step of capturing a tomographic image of the manufactured semiconductor device; a fifth step of comparing a shape and a dimension of a unit included in the semiconductor device between the tomographic image and the corrected CAD data; and a sixth step of determining that the matching trial object is failed when a difference therebetween as a result of the comparison in the fifth step is equal to or larger than a predetermined amount.
    Type: Application
    Filed: January 11, 2017
    Publication date: August 24, 2017
    Inventors: Yoshihiro ONO, Kenji SAKATA
  • Patent number: 9608487
    Abstract: A winding wire (14) includes a first coil (15) formed by being wound N/2+? times between two predetermined slots (13) present in positions which are point-symmetrical with respect to a rotating shaft, and a second coil (16) formed by being wound N/2?? times between the two predetermined slots (13) which are the same as those between which the first coil (15) is formed, when a predetermined number of turns of the winding wire (14) between the predetermined slots is N.
    Type: Grant
    Filed: October 17, 2012
    Date of Patent: March 28, 2017
    Assignee: Mitsuba Corporation
    Inventors: Kenji Sakata, Akio Hoshino
  • Publication number: 20170047296
    Abstract: In a semiconductor device according to an embodiment, a second semiconductor chip is mounted on a first rear surface of a first semiconductor chip. Also, the first rear surface of the first semiconductor chip includes a first region in which a plurality of first rear electrodes electrically connected to the second semiconductor chip via a protrusion electrode are formed and a second region which is located on a peripheral side relative to the first region and in which a first metal pattern is formed. In addition, a protrusion height of the first metal pattern with respect to the first rear surface is smaller than a protrusion height of each of the plurality of first rear electrodes with respect to the first rear surface.
    Type: Application
    Filed: April 14, 2014
    Publication date: February 16, 2017
    Inventors: Shinji WATANABE, Tsuyoshi KIDA, Yoshihiro ONO, Kentaro MORI, Kenji SAKATA, Yusuke YAMADA
  • Publication number: 20160350717
    Abstract: A group supporting apparatus and related computer readable recording medium to execute a process including: collecting input contents, which are input by participants via terminals, from the terminals; arranging the collected input contents into input content groups based on groups to which the participants belong; setting a representative flag on each of representative input contents selected from the respective input content groups; extracting the representative input contents and matching input contents, which match a predetermined extracting condition and are different from the representative input contents, from the collected input contents; and displaying a list of the representative input contents and the matching input contents on a display device that all the participants are able to view at a same time.
    Type: Application
    Filed: August 10, 2016
    Publication date: December 1, 2016
    Applicant: FUJITSU LIMITED
    Inventors: Hidehiko MAYUMI, Toshio TANAKA, Takeaki KOBAYASHI, Takehiro NABAE, Kenji SAKATA
  • Patent number: 9449069
    Abstract: A method of supporting a group work includes collecting input contents, which are input by participants via terminals, from the terminals; arranging the collected input contents into input content groups based on groups to which the participants belong; setting a representative flag on each of representative input contents selected from the respective input content groups; extracting the representative input contents and matching input contents, which match a predetermined extracting condition and are different from the representative input contents, from the collected input contents; and displaying a list of the representative input contents and the matching input contents on a display device that all the participants are able to view at a same time.
    Type: Grant
    Filed: December 26, 2012
    Date of Patent: September 20, 2016
    Assignee: FUJITSU LIMITED
    Inventors: Hidehiko Mayumi, Toshio Tanaka, Takeaki Kobayashi, Takehiro Nabae, Kenji Sakata
  • Publication number: 20160260680
    Abstract: A method for manufacturing a semiconductor device includes the steps of mounting a Si interposer over a printed wiring substrate, plasma-cleaning an upper surface of the Si interposer, disposing an NCF over the upper surface of the Si interposer, and mounting a semiconductor chip over the upper surface of the Si interposer through the NCF. Also, the method includes the step of electrically coupling each of plural electrodes of a second substrate and each of plural electrode pads of the semiconductor chip with each other through plural bump electrodes by reflow, and the surface of the Si interposer is plasma-cleaned before attaching the NCF to the Si interposer.
    Type: Application
    Filed: March 2, 2016
    Publication date: September 8, 2016
    Inventors: Kenji SAKATA, Tsuyoshi KIDA, Yoshihiro ONO