Patents by Inventor Kenji Shirakawa
Kenji Shirakawa has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 12136886Abstract: For power transfer from a first DC part to a second DC part in a dual active bridge (DAB) converter by stepping up a voltage, the second bridge circuit includes a period in which a secondary winding of an insulated transformer and the second DC part conduct and a period in which ends of the secondary winding of the insulated transformer are short-circuited in the second bridge circuit. A control circuit fixes a phase difference between a first leg a the second leg, variably controls a simultaneous off period of a fifth switching element and a sixth switching element, and variably controls a simultaneous off period of a seventh switching element and an eighth switching element.Type: GrantFiled: June 22, 2020Date of Patent: November 5, 2024Assignee: Panasonic Intellectual Property Management Co., Ltd.Inventors: Shogo Hirota, Kenji Hanamura, Takashi Shirakawa
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Publication number: 20240311372Abstract: A method for executing query processing includes, in response to a query from a host, generating a task graph indicating a plurality of task sequences, each of the task sequences capable f performing query processing corresponding to the query. The sequences includes a first sequence that outputs data in a first compression state to a one of output targets, and a second sequence of tasks that outputs the data in a second compression state different from the first compression state to the one of the output targets. The method further includes determining a processing cost for each of the task sequences, selecting one of the task sequences in accordance with the determined processing cost, and performing the query processing corresponding to the query in accordance with the selected task sequence.Type: ApplicationFiled: February 29, 2024Publication date: September 19, 2024Inventors: Daiki WATANABE, Takeshi ISHIHARA, Kenji SHIRAKAWA
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Publication number: 20230305898Abstract: In a resource allocation control device, a dependency information acquisition unit acquires dependency information indicating subdivided process items that constitute a task and a dependency of the process items. A resource information acquisition unit acquires resource information that is information indicating what kind of resource allocation is possible for the task. A score calculation unit calculates a score for a processing procedure of the process items based on the dependency information, and the resource allocation. A search unit searches for a combination of which the score is excellent. An output unit outputs resource allocation corresponding to the excellent score found by the search unit.Type: ApplicationFiled: August 26, 2022Publication date: September 28, 2023Inventors: Daiki WATANABE, Kenji SHIRAKAWA, Takeshi ISHIHARA
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Publication number: 20170351608Abstract: According to one embodiment, a host device is provided. The host device includes a processor that stores a log of a file in plurality of storages using a log -structured file system. The processor selects in which of the plural storages to store a log which is determined to be live in garbage collection which is a process of determining whether the log is live.Type: ApplicationFiled: March 6, 2017Publication date: December 7, 2017Applicant: TOSHIBA MEMORY CORPORATIONInventor: Kenji SHIRAKAWA
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Patent number: 7673155Abstract: A tamper resistant microprocessor has a task state table for assigning a task identifier to a task that can take a plurality of states, and storing a state of the task in correspondence to the task identifier; a task register for storing the task identifier of a currently executed task; an interface for reading a program stored in a form encrypted by using a program key at an external memory, in units of cache lines, when a request for the task is made; an encryption processing unit for generating decryption keys that are different for different cache lines, according to the program key, and decrypt a content read by the interface; a cache memory formed by a plurality of cache lines each having a tag, for storing the task identifier corresponding to a decryption key used in decrypting each cache line in the tag of each cache line; and an access check unit for comparing the task identifier stored in the tag of each cache line with a value of the task register, and discarding a content of each cache line when tType: GrantFiled: May 9, 2008Date of Patent: March 2, 2010Assignee: Kabushiki Kaisha ToshibaInventors: Mikio Hashimoto, Kensaku Fujimoto, Kenji Shirakawa
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Patent number: 7673152Abstract: In a microprocessor, a program key for decrypting a program and a data key for encrypting/decrypting data processed by the program are handled as cryptographically inseparable pair inside the microprocessor, so that it becomes possible for the microprocessor to protect processes that actually execute the program, without an intervention of the operating system, and it becomes possible to conceal secret information of the program not only from the other user program but also from the operating system.Type: GrantFiled: January 20, 2006Date of Patent: March 2, 2010Assignee: Kabushiki Kaisha ToshibaInventors: Kenji Shirakawa, Mikio Hashimoto, Keiichi Teramoto, Satoshi Ozaki, Kensaku Fujimoto
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Patent number: 7657760Abstract: In the method for sharing encrypted data region among two or more processes on a tamper resistant processor, one process creates the encrypted data region to be shared according to the common key generated as a result of the safe key exchange, and the other process maps that region to its own address space or process space. The address information of the shared encrypted data region and the common key of each process are set in relation in the encrypted attribute register inside the tamper resistant processor, so that it is possible to share the encrypted data region safely.Type: GrantFiled: October 3, 2006Date of Patent: February 2, 2010Assignee: Kabushiki Kaisha ToshibaInventors: Keiichi Teramoto, Mikio Hashimoto, Kenji Shirakawa, Satoshi Ozaki, Kensaku Fujimoto
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Publication number: 20090006864Abstract: A tamper resistant microprocessor has a task state table for assigning a task identifier to a task that can take a plurality of states, and storing a state of the task in correspondence to the task identifier; a task register for storing the task identifier of a currently executed task; an interface for reading a program stored in a form encrypted by using a program key at an external memory, in units of cache lines, when a request for the task is made; an encryption processing unit for generating decryption keys that are different for different cache lines, according to the program key, and decrypt a content read by the interface; a cache memory formed by a plurality of cache lines each having a tag, for storing the task identifier corresponding to a decryption key used in decrypting each cache line in the tag of each cache line; and an access check unit for comparing the task identifier stored in the tag of each cache line with a value of the task register, and discarding a content of each cache line when tType: ApplicationFiled: May 9, 2008Publication date: January 1, 2009Applicant: KABUSHIKI KAISHA TOSHIBAInventors: Mikio Hashimoto, Kensaku Fujimoto, Kenji Shirakawa
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Patent number: 7424622Abstract: A tamper resistant microprocessor has a task state table for assigning a task identifier to a task that can take a plurality of states, and storing a state of the task in correspondence to the task identifier; a task register for storing the task identifier of a currently executed task; an interface for reading a program stored in a form encrypted by using a program key at an external memory, in units of cache lines, when a request for the task is made; an encryption processing unit for generating decryption keys that are different for different cache lines, according to the program key, and decrypt a content read by the interface; a cache memory formed by a plurality of cache lines each having a tag, for storing the task identifier corresponding to a decryption key used in decrypting each cache line in the tag of each cache line; and an access check unit for comparing the task identifier stored in the tag of each cache line with a value of the task register, and discarding a content of each cache line when tType: GrantFiled: September 30, 2002Date of Patent: September 9, 2008Assignee: Kabushiki Kaisha ToshibaInventors: Mikio Hashimoto, Kensaku Fujimoto, Kenji Shirakawa
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Patent number: 7353404Abstract: Under a multi-task environment, a tamper resistant microprocessor saves a context information for one program whose execution is to be interrupted, where the context information contains information indicating an execution state of that one program and the execution code encryption key of that one program. An execution of that one program can be restarted by recovering the execution state of that one program from the saved context information. The context information can be encrypted by using the public key of the microprocessor, and then decrypted by using the secret key of the microprocessor.Type: GrantFiled: March 4, 2005Date of Patent: April 1, 2008Assignee: Kabushiki Kaisha ToshibaInventors: Mikio Hashimoto, Keiichi Teramoto, Takeshi Saito, Kenji Shirakawa, Kensaku Fujimoto
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Publication number: 20080046763Abstract: In the method for sharing encrypted data region among two or more processes on a tamper resistant processor, one process creates the encrypted data region to be shared according to the common key generated as a result of the safe key exchange, and the other process maps that region to its own address space or process space. The address information of the shared encrypted data region and the common key of each process are set in relation in the encrypted attribute register inside the tamper resistant processor, so that it is possible to share the encrypted data region safely.Type: ApplicationFiled: October 3, 2006Publication date: February 21, 2008Applicant: KABUSHIKI KAISHA TOSHIBAInventors: Keiichi TERAMOTO, Mikio Hashimoto, Kenji Shirakawa, Satoshi Ozaki, Kensaku Fujimoto
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Patent number: 7270193Abstract: A scheme for distributing executable programs through a network from a program distribution device to a client device having a tamper resistant processor which is provided with a unique secret key and a unique public key corresponding to the unique secret key in advance is disclosed. In this scheme, a first communication path is set up between the program distribution device and the client device, and a second communication path directly connecting the program distribution device and the tamper resistant processor is set up on the first communication path. Then, the encrypted program is transmitted from the program distribution device to the tamper resistant processor through the second communication path.Type: GrantFiled: February 13, 2001Date of Patent: September 18, 2007Assignee: Kabushiki Kaisha ToshibaInventors: Mikio Hashimoto, Kensaku Fujimoto, Kenji Shirakawa, Keiichi Teramoto, Takeshi Saito
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Patent number: 7219369Abstract: In an inner memory type tamper resistant microprocessor, a requested secret protection attribute requested for each access target memory page by a task is set and stored exclusively from other tasks, at a time of reading a program into memory pages and executing the program as the task, and a memory secret protection attribute is set and stored for each access target memory page by the task, at a time of executing the task. Then, an access to each access target memory page is refused when the requested secret protection attribute for each access target memory page and the memory secret protection attribute for each access target memory page do not coincide.Type: GrantFiled: March 20, 2003Date of Patent: May 15, 2007Assignee: Kabushiki Kaisha ToshibaInventors: Mikio Hashimoto, Kensaku Yamaguchi, Kenji Shirakawa, Kensaku Fujimoto
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Patent number: 7136488Abstract: In a microprocessor that internally has a microprocessor specific secret key, a key management unit is provided to carry out a key registration for reading out from an external memory a distribution key that is obtained in advance by encrypting the instruction key by using a public key corresponding to the secret key, decrypting the distribution key by using the secret key to obtain the instruction key, and registering the instruction key in correspondence to a specific program identifier for identifying the program into a key table, and to notify a completion of the key registration to the processor core asynchronously by interruption when the key registration is completed.Type: GrantFiled: January 31, 2002Date of Patent: November 14, 2006Assignee: Kabushiki Kaisha ToshibaInventors: Mikio Hashimoto, Kenji Shirakawa, Keiichi Teramoto, Kensaku Fujimoto, Satoshi Ozaki
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Patent number: 7065215Abstract: In a microprocessor, a program key for decrypting a program and a data key for encrypting/decrypting data processed by the program are handled as cryptographically inseparable pair inside the microprocessor, so that it becomes possible for the microprocessor to protect processes that actually execute the program, without an intervention of the operating system, and it becomes possible to conceal secret information of the program not only from the other user program but also from the operating system.Type: GrantFiled: October 30, 2001Date of Patent: June 20, 2006Assignee: Kabushiki Kaisha ToshibaInventors: Kenji Shirakawa, Mikio Hashimoto, Keiichi Teramoto, Satoshi Ozaki, Kensaku Fujimoto
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Publication number: 20060126849Abstract: In a microprocessor, a program key for decrypting a program and a data key for encrypting/decrypting data processed by the program are handled as cryptographically inseparable pair inside the microprocessor, so that it becomes possible for the microprocessor to protect processes that actually execute the program, without an intervention of the operating system, and it becomes possible to conceal secret information of the program not only from the other user program but also from the operating system.Type: ApplicationFiled: January 20, 2006Publication date: June 15, 2006Applicant: KABUSHIKI KAISHA TOSHIBAInventors: Kenji Shirakawa, Mikio Hashimoto, Keiichi Teramoto, Satoshi Ozaki, Kensaku Fujimoto
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Patent number: 7027442Abstract: A packet processing device is formed by a digest information generation unit configured to extract a plurality of prescribed bit sequences from an input packet, and generate a digest information capable of specifying at least a part of a processing to be applied to the input packet, according to values of the plurality of prescribed bit sequences; and a packet processing unit configured to process the input packet using an instruction sequence to be applied to the input packet that is obtained according to the digest information generated by the digest information generation unit, where the digest information generation unit generates the digest information with respect to a next input packet while the packet processing unit carries out a processing for one packet.Type: GrantFiled: September 7, 2004Date of Patent: April 11, 2006Assignee: Kabushiki Kaisha ToshibaInventors: Kenji Shirakawa, Yasuro Shobatake, Toshio Okamoto, Yoshimitsu Shimojo
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Patent number: 6983374Abstract: Under a multi-task environment, a tamper resistant microprocessor saves a context information for one program whose execution is to be interrupted, where the context information contains information indicating an execution state of that one program and the execution code encryption key of that one program. An execution of that one program can be restarted by recovering the execution state of that one program from the saved context information. The context information can be encrypted by using the public key of the microprocessor, and then decrypted by using the secret key of the microprocessor.Type: GrantFiled: February 13, 2001Date of Patent: January 3, 2006Assignee: Kabushiki Kaisha ToshibaInventors: Mikio Hashimoto, Keiichi Teramoto, Takeshi Saito, Kenji Shirakawa, Kensaku Fujimoto
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Publication number: 20050257746Abstract: A clamp member capable of reliably releasing sticking to a substrate with a simple structure, a film deposition apparatus and method, and a semiconductor device manufacturing method using the clamp member are provided. A clamp ring includes an inner flange portion, a rotating shaft arranged at the inner flange portion, and a rotating member. The rotating member is rotatable about the rotating shaft, and has front and rear end portions. The rotating member is arranged such that the front end portion is positioned to face a part of the wafer with a space therebetween when the inner flange portion is holding the wafer. When the rear end portion is pressed against the inner flange portion, the rotating member rotates about the rotating shaft, and thus, the front end portion can press the part of the wafer in a direction away from the inner flange portion.Type: ApplicationFiled: May 20, 2005Publication date: November 24, 2005Inventors: Kenji Shirakawa, Nobuhiro Nishizaki, Kohichi Sekiya, Kazuo Iwami, Masato Toyota
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Publication number: 20050166069Abstract: Under a multi-task environment, a tamper resistant microprocessor saves a context information for one program whose execution is to be interrupted, where the context information contains information indicating an execution state of that one program and the execution code encryption key of that one program. An execution of that one program can be restarted by recovering the execution state of that one program from the saved context information. The context information can be encrypted by using the public key of the microprocessor, and then decrypted by using the secret key of the microprocessor.Type: ApplicationFiled: March 4, 2005Publication date: July 28, 2005Applicant: KABUSHIKI KAISHA TOSHIBAInventors: Mikio Hashimoto, Keiichi Teramoto, Takeshi Saito, Kenji Shirakawa, Kensaku Fujimoto