Abstract: A packet processing device is formed by a digest information generation unit configured to extract a plurality of prescribed bit sequences from an input packet, and generate a digest information capable of specifying at least a part of a processing to be applied to the input packet, according to values of the plurality of prescribed bit sequences; and a packet processing unit configured to process the input packet using an instruction sequence to be applied to the input packet that is obtained according to the digest information generated by the digest information generation unit, where the digest information generation unit generates the digest information with respect to a next input packet while the packet processing unit carries out a processing for one packet.

Abstract: A packet processing device is formed by a digest information generation unit configured to extract a plurality of prescribed bit sequences from an input packet, and generate a digest information capable of specifying at least a part of a processing to be applied to the input packet, according to values of the plurality of prescribed bit sequences; and a packet processing unit configured to process the input packet using an instruction sequence to be applied to the input packet that is obtained according to the digest information generated by the digest information generation unit, where the digest information generation unit generates the digest information with respect to a next input packet while the packet processing unit carries out a processing for one packet.

Abstract: A packet processing device is formed by a digest information generation unit configured to extract a plurality of prescribed bit sequences from an input packet, and generate a digest information capable of specifying at least a part of a processing to be applied to the input packet, according to values of the plurality of proscribed bit sequences; and a packet processing unit configured to process the input packet using an Instruction sequence to be applied to the input packet that is obtained according to the digest information generated by the digest information generation unit, where the digest information generation unit generates the digest information with respect to a next input packet while the packet processing unit carries out a processing for one packet.

Abstract: In an inner memory type tamper resistant microprocessor, a requested secret protection attribute requested for each access target memory page by a task is set and stored exclusively from other tasks, at a time of reading a program into memory pages and executing the program as the task, and a memory secret protection attribute is set and stored for each access target memory page by the task, at a time of executing the task. Then, an access to each access target memory page is refused when the requested secret protection attribute for each access target memory page and the memory secret protection attribute for each access target memory page do not coincide.

Abstract: A multiprocessor system according to the present invention, comprises a plurality of calculation processors which execute tasks by using data stored in a memory; and a control processor which controls execution of the tasks by said calculation processors; wherein said control processor includes: a dependency relation checking part which checks a dependency relation between a plurality of data when executing the tasks; and a scheduling part which performs access to said memory, data transfer from said memory to said calculation processor, and calculation scheduling in said calculation processors.

Abstract: In the method for sharing encrypted data region among two or more processes on a tamper resistant processor, one process creates the encrypted data region to be shared according to the common key generated as a result of the safe key exchange, and the other process maps that region to its own address space or process space. The address information of the shared encrypted data region and the common key of each process are set in relation in the encrypted attribute register inside the tamper resistant processor, so that it is possible to share the encrypted data region safely.

Abstract: A tamper resistant microprocessor has a task state table for assigning a task identifier to a task that can take a plurality of states, and storing a state of the task in correspondence to the task identifier; a task register for storing the task identifier of a currently executed task; an interface for reading a program stored in a form encrypted by using a program key at an external memory, in units of cache lines, when a request for the task is made; an encryption processing unit for generating decryption keys that are different for different cache lines, according to the program key, and decrypt a content read by the interface; a cache memory formed by a plurality of cache lines each having a tag, for storing the task identifier corresponding to a decryption key used in decrypting each cache line in the tag of each cache line; and an access check unit for comparing the task identifier stored in the tag of each cache line with a value of the task register, and discarding a content of each cache line when t

Abstract: In a tamper resistant microprocessor, a processor temporary key in a form of an encryption key of a secret key cryptosystem is generated at every occasion of an initialization of the microprocessor, according to a random number that is generated according to parameters used inside the microprocessor and that is different for different microprocessors. Then, the context is encrypted by using the processor temporary key and saved into the external memory, and recovered from the external memory and decrypted by using the processor temporary key.

Abstract: In a microprocessor that internally has a microprocessor specific secret key, a key management unit is provided to carry out a key registration for reading out from an external memory a distribution key that is obtained in advance by encrypting the instruction key by using a public key corresponding to the secret key, decrypting the distribution key by using the secret key to obtain the instruction key, and registering the instruction key in correspondence to a specific program identifier for identifying the program into a key table, and to notify a completion of the key registration to the processor core asynchronously by interruption when the key registration is completed.

Abstract: In a program distribution system including a source file sending device, an encrypted program distribution device and an execution file receiving device, which are interconnected through a network, the encrypted program distribution device examines the source file received from the source file sending device, and when the source file passes an examination, an execution file of the program is generated from the source file, a public key which is either unique to an execution file receiving device or unique to a processor of the execution file receiving device is received from the execution file receiving device through the network, at least a part of the execution file is encrypted by using the public key, and the execution file is sent to the execution file receiving device.

Abstract: In a microprocessor, a program key for decrypting a program and a data key for encrypting/decrypting data processed by the program are handled as cryptographically inseparable pair inside the microprocessor, so that it becomes possible for the microprocessor to protect processes that actually execute the program, without an intervention of the operating system, and it becomes possible to conceal secret information of the program not only from the other user program but also from the operating system.

Abstract: A plasma processing apparatus mainly comprises a processing chamber (10) formed by a vacuum vessel, a magnetic field forming coil (80) arranged around the processing chamber for forming a rotating magnetic field and gas supply means (101) supplying various gases to the processing chamber (10). The processing chamber (10) is divided into a reaction chamber (44) forming plasma with a partition wall (43) and a buffer chamber (45) discharging externally supplied gases with pressure difference. The reaction chamber (44) includes a high-frequency electrode arranged oppositely to the buffer chamber (45). The gas supply means (101) includes pulse gas valves (63a and 63b) for pulsatively supplying gases to the processing chamber (10). Thus provided are a plasma processing method and a plasma processing apparatus capable of uniformly processing a wafer having a large diameter and reducing RIE lag with respect to a fine etching pattern.

Abstract: Under a multi-task environment, a tamper resistant microprocessor saves a context information for one program whose execution is to be interrupted, where the context information contains information indicating an execution state of that one program and the execution code encryption key of that one program. An execution of that one program can be restarted by recovering the execution state of that one program from the saved context information. The context information can be encrypted by using the public key of the microprocessor, and then decrypted by using the secret key of the microprocessor.

Abstract: A scheme for distributing executable programs through a network from a program distribution device to a client device having a tamper resistant processor which is provided with a unique secret key and a unique public key corresponding to the unique secret key in advance is disclosed. In this scheme, a first communication path is set up between the program distribution device and the client device, and a second communication path directly connecting the program distribution device and the tamper resistant processor is set up on the first communication path. Then, the encrypted program is transmitted from the program distribution device to the tamper resistant processor through the second communication path.

Abstract: A single virtual space management scheme suitable for a distributed system. The single virtual space for arranging programs and/or data among a plurality of computers forming the distributed system are divided into a plurality of regions called memory chapters, and a part of the single virtual space to be managed independently by each computer is requested from each computer in units of these memory chapters. Then, a server allocates one of the memory chapters to each computer in response to each request from each computer, while managing allocations of the memory chapters to the plurality of computers so as not to allocate each one of the memory chapters to more than one computers. Each memory chapter allocated to each computer is independently managed by further dividing each memory chapter into a plurality of sub-regions called memory sections, and carrying out an access protection in units of these memory sections at each computer.

Abstract: There are disclosed apparatus and method for eliminating, by plasma cleaning, reaction products which are generated by etching and stick to an inner wall surface of a chamber. First to third conductive blocks (90a to 90c) are mounted on the inner wall surface of the chamber (50) through an insulator (92). A high-frequency electric field is applied sequentially between a first electrode (61) and the respective conductive blocks (90a to 90c) while a reactive gas is introduced into an internal space (51) of the chamber (50), to produce a plasma of the reactive gas. The reaction products which stick to the respective conductive blocks (90a to 90c) are sequentially gasified by the plasma of the reactive gas and exhausted to the outside of the chamber (50) to be eliminated.

Abstract: Plasma is produced continuously in an etching switching period for switching from a partial plasma etching process to the next partial plasma etching process to thereby proceed with anisotropic plasma etching even in the etching switching period. There is no period in which isotropic etching is performed throughout the process. The time period for executing the partial plasma etching process, which follows the etching switching period, is shortened while throughput is improved.