Abstract: A pin puller includes a coupler to connect a pull rod to an end of a pin. A follower attaches to a tail end of the pin. The coupler may comprise a pair of mating shells having features to engage the pin and pull rod. An actuator is configured to apply tension to the pull rod. The pin puller may be used to remove and install pins and associated bushings in truck suspensions and other applications.

Abstract: A system comprises a plurality of nodes coupled together via a switching device. Each node comprises a processor coupled to a memory. Migration logic in the switching device is configured to migrate segments of each memory to the switching device.

Abstract: A pin puller includes a coupler to connect a pull rod to an end of a pin. A follower attaches to a tail end of the pin. The coupler may comprise a pair of mating shells having features to engage the pin and pull rod. An actuator is configured to apply tension to the pull rod. The pin puller may be used to remove and install pins and associated bushings in truck suspensions and other applications.

Abstract: A middle manager and methods are provided to enable a plurality of host devices to share one or more input/output devices. The middle manager initializes each shared input/output device and binds one or more functions of each input/output device to a specific host node in the system, such that hosts may only access functions to which they are bound. The middle manager may also utilize a configuration register map to translate values from the actual configuration register into a unique modified value for each of the plurality of host devices such that each host device may access and use the shared input/output device regardless of the firmware or operating system operating thereon.

Abstract: A middle manager and methods are provided to enable a plurality of host devices to share one or more input/output devices. The middle manager initializes each shared input/output device and binds one or more functions of each input/output device to a specific host node in the system, such that hosts may only access functions to which they are bound. The middle manager may also utilize a configuration register map to translate values from the actual configuration register into a unique modified value for each of the plurality of host devices such that each host device may access and use the shared input/output device regardless of the firmware or operating system operating thereon.

Abstract: A computer system includes memory modules, a central processing unit and a memory controller. The memory controller is configured to access the memory modules in response to interaction with the central processing unit and define a fault tolerant memory array with the memory modules. Each memory module stores first data represented by second data stored by the other memory modules.

Abstract: A multi-sectional computing device configurable for a plurality of computing worlds, including portable and desktop computing worlds. The technique includes a space saving and configuration technique utilizing multiple joints disposed between multiple sections to facilitate rotational orientation of the sections to adjust for space limitations and other characteristics of a desired environment or computing world. The multiple sections include a display assembly and a housing assembly for computing components.

Abstract: A system comprises a plurality of nodes coupled together via a switching device. Each node comprises a processor coupled to a memory. Migration logic in the switching device is configured to migrate segments of each memory to the switching device.

Abstract: A multi-sectional computing device configurable for a plurality of computing worlds, including portable and desktop computing worlds. The technique includes a space saving and configuration technique utilizing multiple joints disposed between multiple sections to facilitate rotational orientation of the sections to adjust for space limitations and other characteristics of a desired environment or computing world. The multiple sections include a display assembly and a housing assembly for computing components.

Abstract: A computer system includes a plurality of memory modules that contain semiconductor memory, such as DIMMs. The system includes a host/data controller that utilizes an XOR engine to store data and parity information in a striped fashion on the plurality of memory modules to create a redundant array of industry standard DIMMs (RAID). The system supports DIMMs having X4 and X8 configurations. The system also transitions between various states, including a redundant state and a non-redundant state, to facilitate “hot-plug” capabilities utilizing its removable memory cartridges.

Abstract: A pivotable circuit board holder is featured. The pivotable circuit board holder enables a circuit board to be pivoted from a first position, such as the vertical position, to a second position, such as the horizontal position. The circuit board is removed from the circuit board holder when positioned to the second position.

Abstract: A pivotable circuit board holder is featured. The pivotable circuit board holder enables a circuit board to be pivoted from a first position, such as the vertical position, to a second position, such as the horizontal position. The circuit board is removed from the circuit board holder when positioned to the second position.

Abstract: A computer system includes memory modules, a central processing unit and a memory controller. The memory controller is configured to access the memory modules in response to interaction with the central processing unit and define a fault tolerant memory array with the memory modules. Each memory module stores first data represented by second data stored by the other memory modules.

Abstract: A self-orienting logo assembly so that the logo is always in a horizontal orientation. In the preferred embodiments the logo is located on a disk. The disk is weighted or otherwise designed to have its weight distributed nonuniformly. The disk is located inside a housing. The housing is attached to the computer or other equipment bearing the logo. When the housing is located in a vertical plane the disk rotates to allow the logo to remain horizontal. The disk can be rotationally mounted to the housing or can be suspended in liquid. In an alternate embodiment the disk can have a magnet incorporated so that when the disk is in a horizontal orientation it can act as a compass. In another embodiment a portion of the disk is removed and the housing contains an additional logo or wording. The rotation of the disk can then cover or expose the additional logo or wording.

Abstract: A method and system of intrachassis computer component command and control. The existing power rail is used as network connectivity. Further, the CEBus standard (or a CEBus standard modified for the particular power bus) is used to provide platform management functionality. This management functionality is similar to that provided by the proposed IPMI specification. However, the management functionality is implemented intrachassis, that is, it is applied to the internal components of the machine. Particularly advantageous functions, such as rollcall enumeration and command authentication and verification, are included in a preferred embodiment. Further, because these innovative techniques utilize the existing power rail, no additional external cables are required.

Abstract: A processor-based system includes a processing unit. The processing unit includes at least a processor and preferably also a cache memory, a cache memory controller and a numerical coprocessor. The processing unit is reset in response to a system reset signal being asserted at a reset input node and only selected portions of the processing unit are reset in response to a partial-reset signal being asserted at a partial-reset input node. The system can also include a number of other components such as video circuitry, a hard disk drive, bus interface circuitry, a speaker, a keyboard controller and a keyboard.

Abstract: A high speed connection apparatus, method, and system is provided for peripheral components on digital computer systems. The peripheral component interconnect (PCI) specification is used as a baseline for an extended set of commands and attributes. The extended command and the attribute are issued on the bus during the clock cycle immediately after the clock cycle when the initial command was issued. The extended commands and attributes utilize the standard pin connections of conventional PCI devices and buses making the present invention backward-compatible with existing (conventional) PCI devices and legacy computer systems. Alternate embodiments of the present invention utilize a side-band address port (SBA port) to enable multiple targets to receive the same set of data. The conventional PCI command encoding is modified and the extended command is used to qualify the type of transaction and the attributes being used by the initiator of the transaction.

Abstract: A computer system includes memory modules, a central processing unit and a memory controller. The memory controller is configured to access the memory modules in response to interaction with the central processing unit and define a fault tolerant memory array with the memory modules. Each memory module stores first data represented by second data stored by the other memory modules.

Abstract: A scheme may be used to remove or replace a processor in a multiprocessor computer without the need for turning the computer off to replace the processor. In this scheme, the bus to which the processor is coupled is identified so that all processors coupled to the bus may be placed in sleep mode. This act does not alter the normal operation of processors that may be coupled to another bus. Once the processors are in sleep mode, the processor may be removed or replaced. Afterward, all processors may be returned to normal operation.

Abstract: A multiprocessor computer includes a fault detection scheme which detects and identifies the failure of one of the processors. Each processor is assigned a write location, which may be a unique register. During normal computer operation, each processor intermittently performs a test and stores the results of the test in the assigned write location. The stored results are compared to expected results, and an error signal is generated if the stored results differ from the expected results to indicate that one of the processors has failed.