Patents by Inventor Kenneth J. Eldredge
Kenneth J. Eldredge has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 11875859Abstract: A memory device might include control circuitry configured to cause the memory device to compare input data to data stored in memory cells connected to a data line, cause a first level of current to flow from the data line in response to a mismatch between one digit of the input data and data stored in a respective pair of memory cells, cause a second level of current to flow from the data line in response to a mismatch between a different digit of the input data and the data stored in a respective pair of memory cells, compare a representation of a level of current in the data line to a reference, and deem the input data to potentially match or not match the data stored in the plurality of memory cells in response to the comparison.Type: GrantFiled: March 2, 2021Date of Patent: January 16, 2024Assignee: Micron Technology, Inc.Inventors: Kenneth J. Eldredge, Frankie F. Roohparvar, Luca De Santis, Tommaso Vali
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Patent number: 11682458Abstract: Memory devices might include a plurality of memory cell pairs each configured to be programmed to store a digit of data; and control circuitry configured to cause the memory device to compare the stored digit of data of each memory cell pair to a received digit of data, determine whether a match condition or a no-match condition is indicated between the stored digit of data of each memory cell pair and the received digit of data, and deem a match condition to be met between the received digit of data and the stored digits of data of the plurality of memory cell pairs in response to a match condition being determined for a majority of memory cell pairs of the plurality of memory cell pairs.Type: GrantFiled: December 6, 2021Date of Patent: June 20, 2023Assignee: Micron Technology, Inc.Inventors: Luca De Santis, Tommaso Vali, Kenneth J. Eldredge, Vishal Sarin
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Publication number: 20220122665Abstract: Memory devices might include a plurality of memory cell pairs each configured to be programmed to store a digit of data; and control circuitry configured to cause the memory device to compare the stored digit of data of each memory cell pair to a received digit of data, determine whether a match condition or a no-match condition is indicated between the stored digit of data of each memory cell pair and the received digit of data, and deem a match condition to be met between the received digit of data and the stored digits of data of the plurality of memory cell pairs in response to a match condition being determined for a majority of memory cell pairs of the plurality of memory cell pairs.Type: ApplicationFiled: December 6, 2021Publication date: April 21, 2022Applicant: MICRON TECHNOLOGY, INC.Inventors: Luca De Santis, Tommaso Vali, Kenneth J. Eldredge, Vishal Sarin
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Patent number: 11205481Abstract: Memory devices might include control circuitry that, when checking for a match of a stored digit of data and a received digit of data, might be configured to cause the memory device to apply a first voltage level to a control gate of a first memory cell of a memory cell pair, apply a second voltage level different than the first voltage level to a control gate of a second memory cell of that memory cell pair, determine whether that memory cell pair is deemed to be activated or deactivated in response to applying the first and second voltage levels, and deem a match between the stored digit of data and a received digit of data in response, in part, to whether that memory cell pair is deemed to be deactivated.Type: GrantFiled: March 31, 2021Date of Patent: December 21, 2021Assignee: Micron Technology, Inc.Inventors: Luca De Santis, Tommaso Vali, Kenneth J. Eldredge, Vishal Sarin
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Patent number: 11074982Abstract: Memory having an array of memory cells and configured to store a first value representative of a characteristic sensed from a first data line, store a second value representative of the characteristic sensed from a second data line, perform an operation on the first value and the data value at a first logic circuitry, and perform an operation on an output of the first logic circuitry and a threshold data value at a second logic circuitry.Type: GrantFiled: August 10, 2020Date of Patent: July 27, 2021Assignee: Micron Technology, Inc.Inventors: Tommaso Vali, Kenneth J. Eldredge, Frankie F. Roohparvar, Luca De Santis
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Publication number: 20210217475Abstract: Memory devices might include control circuitry that, when checking for a match of a stored digit of data and a received digit of data, might be configured to cause the memory device to apply a first voltage level to a control gate of a first memory cell of a memory cell pair, apply a second voltage level different than the first voltage level to a control gate of a second memory cell of that memory cell pair, determine whether that memory cell pair is deemed to be activated or deactivated in response to applying the first and second voltage levels, and deem a match between the stored digit of data and a received digit of data in response, in part, to whether that memory cell pair is deemed to be deactivated.Type: ApplicationFiled: March 31, 2021Publication date: July 15, 2021Applicant: MICRON TECHNOLOGY, INC.Inventors: Luca De Santis, Tommaso Vali, Kenneth J. Eldredge, Vishal Sarin
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Publication number: 20210183452Abstract: A memory device might include control circuitry configured to cause the memory device to compare input data to data stored in memory cells connected to a data line, cause a first level of current to flow from the data line in response to a mismatch between one digit of the input data and data stored in a respective pair of memory cells, cause a second level of current to flow from the data line in response to a mismatch between a different digit of the input data and the data stored in a respective pair of memory cells, compare a representation of a level of current in the data line to a reference, and deem the input data to potentially match or not match the data stored in the plurality of memory cells in response to the comparison.Type: ApplicationFiled: March 2, 2021Publication date: June 17, 2021Applicant: MICRON TECHNOLOGY, INC.Inventors: Kenneth J. Eldredge, Frankie F. Roohparvar, Luca De Santis, Tommaso Vali
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Patent number: 10984864Abstract: Methods include receiving a pattern to be searched in a memory having a plurality of sets of memory elements with each set coupled to a separate data line and corresponding to a same set of bit positions of the pattern. Methods further include receiving a pattern of data to be programmed into a memory, programming a first data state into one memory cell of each cell pair of a plurality of cell pairs of a memory array, and programing a second data state into another memory cell of each cell pair of the plurality of cell pairs for each bit position of the pattern. Memory configured to facilitate such methods include a plurality of cell pairs, each cell pair of the plurality of cell pairs programmed to store a same bit of data corresponding to a particular bit position of a pattern to be searched in the memory.Type: GrantFiled: July 22, 2019Date of Patent: April 20, 2021Assignee: Micron Technology, Inc.Inventors: Luca De Santis, Tommaso Vali, Kenneth J. Eldredge, Vishal Sarin
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Patent number: 10950312Abstract: Methods of operating a memory device include comparing input data to data stored in memory cells coupled to a data line, comparing a representation of a level of current in the data line to a reference, and determining that the input data potentially matches the data stored in the memory cells when the representation of the level of current in the data line is less than the reference. Methods of operating a memory device further include comparing input data to first data and to second data stored in memory cells coupled to a first data line or to a second data line, respectively, comparing representations of the levels of current in the first data line and in the second data line to a first reference and to a different second reference, and deeming one to be a closer match to the input data in response to results of the comparisons.Type: GrantFiled: July 1, 2019Date of Patent: March 16, 2021Assignee: Micron Technology, Inc.Inventors: Kenneth J. Eldredge, Frankie F. Roohparvar, Luca De Santis, Tommaso Vali
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Publication number: 20200372960Abstract: Memory having an array of memory cells and configured to store a first value representative of a characteristic sensed from a first data line, store a second value representative of the characteristic sensed from a second data line, perform an operation on the first value and the data value at a first logic circuitry, and perform an operation on an output of the first logic circuitry and a threshold data value at a second logic circuitry.Type: ApplicationFiled: August 10, 2020Publication date: November 26, 2020Applicant: MICRON TECHNOLOGY, INC.Inventors: Tommaso Vali, Kenneth J. Eldredge, Frankie F. Roohparvar, Luca De Santis
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Patent number: 10770152Abstract: Methods of operating a memory device include comparing input data to data stored in strings of series-connected memory cells coupled to a data line, generating a respective resistance in series with each string of series-connected memory cells while comparing the plurality of digits of input data to the stored data, comparing a representation of a level of current in the data line to a reference, deeming the input data to match the stored data in response to the representation of the level of current in the data line being less than the reference, and deeming the input data to not match the stored data in response to the representation of the level of current in the data line being greater than the reference.Type: GrantFiled: November 5, 2018Date of Patent: September 8, 2020Assignee: Micron Technology, Inc.Inventors: Kenneth J. Eldredge, Frankie F. Roohparvar, Luca De Santis, Tommaso Vali
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Patent number: 10741258Abstract: Memory having an array of memory cells and a controller for access of the array of memory cells that is configured to generate a data value indicative of a level of a property sensed from a data line while applying potentials to control gates of memory cells of more than one string of series-connected memory cells connected to that data line.Type: GrantFiled: July 18, 2019Date of Patent: August 11, 2020Assignee: Micron Technology, Inc.Inventors: Tommaso Vali, Kenneth J. Eldredge, Frankie F. Roohparvar, Luca De Santis
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Patent number: 10712960Abstract: Memory devices, and methods of operating similar memory devices, include an array of memory cells comprising a plurality of access lines each configured for biasing control gates of a respective plurality of memory cells of the array of memory cells, wherein the respective plurality of memory cells for one access line of the plurality of access lines is mutually exclusive from the respective plurality of memory cells for each remaining access line of the plurality of access lines, and a controller having a plurality of selectively-enabled operating modes and configured to selectively operate the memory device using two or more concurrently enabled operating modes of the plurality of selectively-enabled operating modes for access of the array of memory cells, with each of the enabled operating modes of the two of more concurrently enabled operating modes utilizing an assigned respective portion of the array of memory cells.Type: GrantFiled: October 22, 2018Date of Patent: July 14, 2020Assignee: Micron Technology, Inc.Inventors: Frankie F. Roohparvar, Luca De Santis, Tommaso Vali, Kenneth J. Eldredge
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Patent number: 10622072Abstract: Methods include receiving a pattern to be searched in a memory having a plurality of sets of memory elements with each set coupled to a separate data line and corresponding to a same set of bit positions of the pattern. Methods further include receiving a pattern of data to be programmed into a memory, programming a first data state into one memory cell of each cell pair of a plurality of cell pairs of a memory array, and programming a second data state into another memory cell of each cell pair of the plurality of cell pairs for each bit position of the pattern. Memory configured to facilitate such methods include a plurality of cell pairs, each cell pair of the plurality of cell pairs programmed to store a same bit of data corresponding to a particular bit position of a pattern to be searched in the memory.Type: GrantFiled: June 27, 2018Date of Patent: April 14, 2020Assignee: Micron Technology, Inc.Inventors: Luca De Santis, Tommaso Vali, Kenneth J. Eldredge, Vishal Sarin
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Patent number: 10529430Abstract: Methods of operating a memory device include comparing input data to data stored in memory cells coupled to a data line, comparing a representation of a level of current in the data line to a reference, and determining that the input data potentially matches the data stored in the memory cells when the representation of the level of current in the data line is less than the reference. Methods of operating a memory device further include comparing input data to first data and to second data stored in memory cells coupled to a first data line or to a second data line, respectively, comparing representations of the levels of current in the first data line and in the second data line to a first reference and to a different second reference, and deeming one to be a closer match to the input data in response to results of the comparisons.Type: GrantFiled: November 5, 2018Date of Patent: January 7, 2020Assignee: Micron Technology, Inc.Inventors: Kenneth J. Eldredge, Frankie F. Roohparvar, Luca De Santis, Tommaso Vali
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Patent number: 10482972Abstract: Memories include a data line, a plurality of strings of series-connected memory cells selectively connected to the data line, a plurality of first access lines each coupled to a control gate of a respective memory cell of each string of series-connected memory cells of the plurality of strings of series-connected memory cells, and a plurality of second access lines each coupled to a control gate of a respective memory cell of a respective string of series-connected memory cells of the plurality of strings of series-connected memory cells.Type: GrantFiled: May 16, 2019Date of Patent: November 19, 2019Assignee: Micron Technology, Inc.Inventors: Luca De Santis, Tommaso Vali, Kenneth J. Eldredge, Frankie F. Roohparvar
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Publication number: 20190348117Abstract: Methods include receiving a pattern to be searched in a memory having a plurality of sets of memory elements with each set coupled to a separate data line and corresponding to a same set of bit positions of the pattern. Methods further include receiving a pattern of data to be programmed into a memory, programming a first data state into one memory cell of each cell pair of a plurality of cell pairs of a memory array, and programing a second data state into another memory cell of each cell pair of the plurality of cell pairs for each bit position of the pattern. Memory configured to facilitate such methods include a plurality of cell pairs, each cell pair of the plurality of cell pairs programmed to store a same bit of data corresponding to a particular bit position of a pattern to be searched in the memory.Type: ApplicationFiled: July 22, 2019Publication date: November 14, 2019Applicant: MICRON TECHNOLOGY, INC.Inventors: Luca De Santis, Tommaso Vali, Kenneth J. Eldredge, Vishal Sarin
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Publication number: 20190341115Abstract: Memory having an array of memory cells and a controller for access of the array of memory cells that is configured to generate a data value indicative of a level of a property sensed from a data line while applying potentials to control gates of memory cells of more than one string of series-connected memory cells connected to that data line.Type: ApplicationFiled: July 18, 2019Publication date: November 7, 2019Applicant: MICRON TECHNOLOGY, INC.Inventors: Tommaso Vali, Kenneth J. Eldredge, Frankie F. Roohparvar, Luca De Santis
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Publication number: 20190325971Abstract: Methods of operating a memory device include comparing input data to data stored in memory cells coupled to a data line, comparing a representation of a level of current in the data line to a reference, and determining that the input data potentially matches the data stored in the memory cells when the representation of the level of current in the data line is less than the reference. Methods of operating a memory device further include comparing input data to first data and to second data stored in memory cells coupled to a first data line or to a second data line, respectively, comparing representations of the levels of current in the first data line and in the second data line to a first reference and to a different second reference, and deeming one to be a closer match to the input data in response to results of the comparisons.Type: ApplicationFiled: July 1, 2019Publication date: October 24, 2019Applicant: MICRON TECHNOLOGY, INC.Inventors: Kenneth J. Eldredge, Frankie F. Roohparvar, Luca De Santis, Tommaso Vali
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Publication number: 20190272877Abstract: Memories include a data line, a plurality of strings of series-connected memory cells selectively connected to the data line, a plurality of first access lines each coupled to a control gate of a respective memory cell of each string of series-connected memory cells of the plurality of strings of series-connected memory cells, and a plurality of second access lines each coupled to a control gate of a respective memory cell of a respective string of series-connected memory cells of the plurality of strings of series-connected memory cells.Type: ApplicationFiled: May 16, 2019Publication date: September 5, 2019Applicant: MICRON TECHNOLOGY, INC.Inventors: Luca De Santis, Tommaso Vali, Kenneth J. Eldredge, Frankie F. Roohparvar