Abstract: A Magnetic Random Access Memory (“MRAM”) device includes an array of memory cells. The device generates reference signals that can be used to determine the resistance states of each memory cell in the array, despite variations in resistance due to manufacturing tolerances and other factors such as temperature gradients across the array, electromagnetic interference and aging.

Abstract: A write circuit for a large array of memory cells of a Magnetic Random Access Memory (“MRAM”) device. The write circuit can provide a controllable, bi-directional write current to selected word and bit lines without exceeding breakdown limits of the memory cells. Additionally, the write circuit can spread out the write currents over time to reduce peak currents.

Abstract: A Magnetic Random Access Memory (“MRAM”) device includes an array of memory cells. The device generates reference signals that can be used to determine the resistance states of each memory cell in the array, despite variations in resistance due to manufacturing tolerances and other factors such as temperature gradients across the array, electromagnetic interference and aging.

Abstract: A Magnetic Random Access Memory (“MRAM”) device includes an array of memory cells. The device generates reference signals that can be used to determine the resistance states of each memory cell in the array, despite variations in resistance due to manufacturing tolerances and other factors such as temperature gradients across the array, electromagnetic interference and aging.

Abstract: A write circuit for a large array of memory cells of a Magnetic Random Access Memory (“MRAM”) device. The write circuit can provide a controllable, bi-directional write current to selected word and bit lines without exceeding breakdown limits of the memory cells. Additionally, the write circuit can spread out the write currents over time to reduce peak currents.

Abstract: An operational amplifier includes transistors for providing a controlled current path. At least one of the transistors is in an isolated well in a substrate. Offset of the operational amplifier is corrected by applying a back gate bias voltage to at least one isolated well and changing impedance of the transistors. The proper back gate bias voltage and transistor impedance are determined by incrementally adjusting the back gate bias voltage and then incrementally adjusting the transistor impedance. Calibration values are stored in register memory. Such calibration may be performed by an auto offset calibration process.

Abstract: A write circuit for a large array of memory cells of a Magnetic Random Access Memory (“MRAM”) device. The write circuit can provide a controllable, bi-directional write current to selected word and bit lines without exceeding breakdown limits of the memory cells. Additionally, the write circuit can spread out the write currents over time to reduce peak currents.

Abstract: Resistance of a selected memory cell in a Magnetic Random Access Memory (“MRAM”) device is sensed by a read circuit including a direct injection charge amplifier, an integrator capacitor and a digital sense amplifier. The direct injection charge amplifier supplies current to the integrator capacitor while maintaining an equipotential voltage on non-selected memory cells in the MRAM device. As the direct injection charge amplifier applies a fixed voltage to the selected memory cell, the sense amplifier measures integration time of a signal on the integrator. The signal integration time indicates whether the memory cell MRAM resistance is at a first state (R) or a second state (R+&Dgr;R).