Patents by Inventor Kenneth J. Stein

Kenneth J. Stein has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 8564074
    Abstract: A semiconductor device is disclosed. The semiconductor device includes a semiconductor substrate including: a high-K dielectric region; a blocking region disposed against at least one surface of the high-K dielectric region and adapted to form an oxidized layer in response to exposure to oxygen; and an oxygen rich region disposed against the blocking region such that the blocking region is interposed between the oxygen rich region and the high-K dielectric region.
    Type: Grant
    Filed: November 29, 2011
    Date of Patent: October 22, 2013
    Assignee: International Business Machines Corporation
    Inventors: Terence B. Hook, Vijay Narayanan, Jay M. Shah, Melanie J. Sherony, Kenneth J. Stein, Helen H. Wang, Chendong Zhu
  • Publication number: 20130134545
    Abstract: A semiconductor device is disclosed. The semiconductor device includes a semiconductor substrate including: a high-K dielectric region; a blocking region disposed against at least one surface of the high-K dielectric region and adapted to form an oxidized layer in response to exposure to oxygen; and an oxygen rich region disposed against the blocking region such that the blocking region is interposed between the oxygen rich region and the high-K dielectric region.
    Type: Application
    Filed: November 29, 2011
    Publication date: May 30, 2013
    Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Terence B. Hook, Vijay Narayanan, Jay M. Shah, Melanie J. Sherony, Kenneth J. Stein, Helen H. Wang, Chendong Zhu
  • Patent number: 8106462
    Abstract: An integrated circuit structure includes a substrate and at least one pair of complementary transistors on or in the substrate. The pair of complementary transistors comprises a first transistor and a second transistor. The structure also includes a first stress-producing layer on the first transistor and the second transistor, and a second stress-producing layer on the first stress-producing layer over the first transistor and the second transistor. The first stress-producing layer applies tensile strain force on the first transistor and the second transistor. The second stress-producing layer applies compressive strain force on the first stress-producing layer, the first transistor, and the second transistor.
    Type: Grant
    Filed: January 14, 2010
    Date of Patent: January 31, 2012
    Assignees: International Business Machines Corporation, Freescale Semiconductor, Inc., Infineon Technologies North America Corp., Chartered Semiconductor Manufacturing Ltd.
    Inventors: Xiangdong Chen, Weipeng Li, Anda C. Mocuta, Dae-Gyu Park, Melanie J. Sherony, Kenneth J. Stein, Haizhou Yin, Franck Arnaud, Jin-Ping Han, Laegu Kang, Yong Meng Lee, Young Way Teh, Voon-Yew Thean, Da Zhang
  • Patent number: 8062951
    Abstract: An epitaxial layer of silicon (Si) or silicon-germanium (SiGe) extends over the edge of silicon trench isolation (STI), thereby increasing the effective width of an active silicon region (RX) bordered by the STI. The RX region may have a <100> crystal orientation. An effective width of an FET device formed in the RX region may be increased, therefore performance may be improved with same density. Isolation may not be degraded since RX-to-RX distance is same at bottom. Junction capacitance may be reduced since part of the RX is on STI.
    Type: Grant
    Filed: December 10, 2007
    Date of Patent: November 22, 2011
    Assignee: International Business Machines Corporation
    Inventors: Xiangdong Chen, Kenneth J. Stein, Thomas A. Wallner
  • Patent number: 8004060
    Abstract: A metal layer and a semiconductor layer are sequentially deposited on a substrate. The semiconductor layer and the metal layer are lithographically patterned to form a stack of a semiconductor portion and a metal gate portion, which is preferably performed concurrently with formation of at least one metal gate stack. In one embodiment, the size of the semiconductor portion is reduced and a metal semiconductor alloy portion is formed on the semiconductor portion by metallization. In a first electrical antifuse formed thereby, the metal semiconductor alloy portion may be electromigrated to form a short between the metal semiconductor alloy portion and the metal gate portion. In another embodiment, two disjoined metal semiconductor alloy portions are formed on the semiconductor portion. In a second electrical antifuse formed thereby, the metal semiconductor alloy portion may be electromigrated to form a short between the two previously disjoined metal semiconductor alloy portions.
    Type: Grant
    Filed: November 29, 2007
    Date of Patent: August 23, 2011
    Assignee: International Business Machines Corporation
    Inventors: Deok-kee Kim, Chandrasekharan Kothandaraman, Dan Moy, Norman W. Robson, John M. Safran, Kenneth J. Stein
  • Publication number: 20110169096
    Abstract: An integrated circuit structure includes a substrate and at least one pair of complementary transistors on or in the substrate. The pair of complementary transistors comprises a first transistor and a second transistor. The structure also includes a first stress-producing layer on the first transistor and the second transistor, and a second stress-producing layer on the first stress-producing layer over the first transistor and the second transistor. The first stress-producing layer applies tensile strain force on the first transistor and the second transistor. The second stress-producing layer applies compressive strain force on the first stress-producing layer, the first transistor, and the second transistor.
    Type: Application
    Filed: January 14, 2010
    Publication date: July 14, 2011
    Applicants: INTERNATIONAL BUSINESS MACHINES CORPORATION, FREESCALE SEMICONDUCTOR, INC., INFINEON TECHNOLOGIES NORTH AMERICA CORP., CHARTERED SEMICONDUCTOR MANUFACTURING LTD.
    Inventors: Xiangdong Chen, Weipeng Li, Anda C. Mocuta, Dae-Gyu Park, Melanie J. Sherony, Kenneth J. Stein, Haizhou Yin, Franck Arnaud, Jin-Ping Han, Laegu Kang, Yong Meng Lee, Young Way Teh, Voon-Yew Thean, Da Zhang
  • Patent number: 7867839
    Abstract: Disclosed are embodiments of a p-type, silicon germanium (SiGe), high-k dielectric-metal gate, metal oxide semiconductor field effect transistor (PFET) having an optimal threshold voltage (Vt), a complementary metal oxide semiconductor (CMOS) device that includes the PFET and methods of forming both the PFET alone and the CMOS device. The embodiments incorporate negatively charged ions (e.g., fluorine (F), chlorine (Cl), bromine (Br), iodine (I), etc.) into the high-k gate dielectric material of the PFET only so as to selectively adjust the negative Vt of the PFET (i.e., so as to reduce the negative Vt of the PFET).
    Type: Grant
    Filed: July 21, 2008
    Date of Patent: January 11, 2011
    Assignee: International Business Machines Corporation
    Inventors: Xiangdong Chen, Jong Ho Lee, Weipeng Li, Dae-Gyu Park, Kenneth J. Stein, Voon-Yew Thean
  • Patent number: 7829427
    Abstract: A method of forming an inductor. The method including: (a) forming a dielectric layer on a top surface of a substrate; after (a), (b) forming a lower trench in the dielectric layer; after (b), (c) forming a resist layer on a top surface of the dielectric layer; after (c), (d) forming an upper trench in the resist layer, the upper trench aligned to the lower trench, a bottom of the upper trench open to the lower trench; and after (d), (e) completely filling the lower trench and at least partially filling the upper trench with a conductor in order to form the inductor.
    Type: Grant
    Filed: November 5, 2009
    Date of Patent: November 9, 2010
    Assignee: International Business Machines Corporation
    Inventors: Daniel C. Edelstein, Panayotis C. Andricacos, John M. Cotte, Hariklia Deligianni, John H. Magerlein, Kevin S. Petrarca, Kenneth J. Stein, Richard P. Volant
  • Publication number: 20100047990
    Abstract: A method of forming an inductor. The method including: (a) forming a dielectric layer on a top surface of a substrate; after (a), (b) forming a lower trench in the dielectric layer; after (b), (c) forming a resist layer on a top surface of the dielectric layer; after (c), (d) forming an upper trench in the resist layer, the upper trench aligned to the lower trench, a bottom of the upper trench open to the lower trench; and after (d), (e) completely filling the lower trench and at least partially filling the upper trench with a conductor in order to form the inductor.
    Type: Application
    Filed: November 5, 2009
    Publication date: February 25, 2010
    Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Daniel C. Edelstein, Panayotis C. Andricacos, John M. Cotte, Hariklia Deligianni, John H. Magerlein, Kevin S. Petrarca, Kenneth J. Stein, Richard P. Volant
  • Publication number: 20100013021
    Abstract: Disclosed are embodiments of a p-type, silicon germanium (SiGe), high-k dielectric-metal gate, metal oxide semiconductor field effect transistor (PFET) having an optimal threshold voltage (Vt), a complementary metal oxide semiconductor (CMOS) device that includes the PFET and methods of forming both the PFET alone and the CMOS device. The embodiments incorporate negatively charged ions (e.g., fluorine (F), chlorine (Cl), bromine (Br), iodine (I), etc.) into the high-k gate dielectric material of the PFET only so as to selectively adjust the negative Vt of the PFET (i.e., so as to reduce the negative Vt of the PFET).
    Type: Application
    Filed: July 21, 2008
    Publication date: January 21, 2010
    Applicants: INTERNATIONAL BUSINESS MACHINES CORPORATION, FREESCALE SEMICONDUCTOR INC., SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Xiangdong Chen, Jong Ho Lee, Weipeng Li, Dae-Gyu Park, Kenneth J. Stein, Voon-Yew Thean
  • Patent number: 7638406
    Abstract: A method of forming an inductor. The method includes: forming a dielectric layer on a substrate; forming a lower trench in the dielectric layer; forming a liner in the lower trench and on the dielectric layer; forming a Cu seed layer over the liner; forming a resist layer on the Cu seed layer; forming an upper trench in the resist layer; electroplating Cu to completely fill the lower trench and at least partially fill the upper trench; removing the resist layer; selectively forming a passivation layer on all exposed Cu surfaces; selectively removing the Cu seed layer from regions of the liner; and removing the thus exposed regions of the liner from the dielectric layer, wherein a top surface of the inductor extends above a top surface of the dielectric layer, the passivation layer remaining on regions of sidewalls of the inductor above the top surface of the dielectric layer.
    Type: Grant
    Filed: December 28, 2005
    Date of Patent: December 29, 2009
    Assignee: International Business Machines Corporation
    Inventors: Daniel C. Edelstein, Panayotis C. Andricacos, John M. Cotte, Hariklia Deligianni, John H. Magerlein, Kevin S. Petrarca, Kenneth J. Stein, Richard P. Volant
  • Publication number: 20090146263
    Abstract: An epitaxial layer of silicon (Si) or silicon-germanium (SiGe) extends over the edge of silicon trench isolation (STI), thereby increasing the effective width of an active silicon region (RX) bordered by the STI. The RX region may have a <100> crystal orientation. An effective width of an FET device formed in the RX region may be increased, therefore performance may be improved with same density. Isolation may not be degraded since RX-to-RX distance is same at bottom. Junction capacitance may be reduced since part of the RX is on STI.
    Type: Application
    Filed: December 10, 2007
    Publication date: June 11, 2009
    Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Xiangdong Chen, Kenneth J. Stein, Thomas A. Wallner
  • Publication number: 20090141533
    Abstract: A metal layer and a semiconductor layer are sequentially deposited on a substrate. The semiconductor layer and the metal layer are lithographically patterned to form a stack of a semiconductor portion and a metal gate portion, which is preferably performed concurrently with formation of at least one metal gate stack. In one embodiment, the size of the semiconductor portion is reduced and a metal semiconductor alloy portion is formed on the semiconductor portion by metallization. In a first electrical antifuse formed thereby, the metal semiconductor alloy portion may be electromigrated to form a short between the metal semiconductor alloy portion and the metal gate portion. In another embodiment, two disjoined metal semiconductor alloy portions are formed on the semiconductor portion. In a second electrical antifuse formed thereby, the metal semiconductor alloy portion may be electromigrated to form a short between the two previously disjoined metal semiconductor alloy portions.
    Type: Application
    Filed: November 29, 2007
    Publication date: June 4, 2009
    Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Deok-kee Kim, Chandrasekharan Kothandaraman, Dan Moy, Norman W. Robson, John M. Safran, Kenneth J. Stein
  • Patent number: 7354872
    Abstract: Methods of forming a high dielectric constant dielectric layer are disclosed including providing a process chamber including a holder for supporting a substrate, introducing a first gas comprising a high dielectric constant (Hi-K) dielectric precursor and an oxygen (O2) oxidant into the process chamber to form a first portion of the high dielectric constant dielectric layer on the substrate, and switching from a flow of the first gas to a flow of a second gas comprising the Hi-K dielectric precursor and an ozone (O3) oxidant to form a second portion of the high dielectric constant dielectric layer on the first portion. In an alternative embodiment, another portion can be formed on the second portion using the oxygen oxidant. The invention increases throughput by at least 20% without reliability or leakage degradation and without the need for additional equipment.
    Type: Grant
    Filed: May 26, 2005
    Date of Patent: April 8, 2008
    Assignee: International Business Machines Corporation
    Inventors: Douglas D. Coolbaugh, Ebenezer E. Eshun, Kenneth J. Stein, Kunal Vaed
  • Patent number: 7193500
    Abstract: An integrated circuit includes a bilayer thin film resistor in which the lower layer is a seed layer that controls the crystal structure of the upper layer. The thickness of the lower layer and the thickness of the upper layer may be chosen to form a resistor with a TCR having a design value.
    Type: Grant
    Filed: September 20, 2004
    Date of Patent: March 20, 2007
    Assignee: International Business Machines Corporation
    Inventors: Anil K. Chinthakindi, Anita Madan, Kenneth J. Stein, Kwong Hon Wong
  • Patent number: 7068138
    Abstract: An inductor and a method of forming and the inductor, the method including: (a) providing a semiconductor substrate; (b) forming a dielectric layer on a top surface of the substrate; (c) forming a lower trench in the dielectric layer; (d) forming a resist layer on a top surface of the dielectric layer; (e) forming an upper trench in the resist layer, the upper trench aligned to the lower trench, a bottom of the upper trench open to the lower trench; and (f) completely filling the lower trench at least partially filling the upper trench with a conductor in order to form the inductor. The inductor including a top surface, a bottom surface and sidewalls, a lower portion of said inductor extending a fixed distance into a dielectric layer formed on a semiconductor substrate and an upper portion extending above said dielectric layer; and means to electrically contact said inductor.
    Type: Grant
    Filed: January 29, 2004
    Date of Patent: June 27, 2006
    Assignee: International Business Machines Corporation
    Inventors: Daniel C. Edelstein, Panayotis C. Andricacos, John M. Cotte, Hariklia Deligianni, John H. Magerlein, Kevin S. Petrarca, Kenneth J. Stein, Richard P. Volant
  • Patent number: 7053460
    Abstract: A passive electrical device includes a first electrical conductor, a second electrical conductor disposed over the first conductor; and a third electrical conductor connecting the first conductor to the second conductor. The said first, second and third conductors are disposed on a semiconductor substrate. The sheet resistivity of the first conductor is approximately equal to the sheet resistivity of the second conductor.
    Type: Grant
    Filed: December 21, 2001
    Date of Patent: May 30, 2006
    Assignee: International Business Machines Corporation
    Inventors: Richard P. Volant, Seshadri Subbanna, Robert A. Groves, John C. Malinowski, Kenneth J. Stein, Kevin S. Petrarca
  • Patent number: 7022246
    Abstract: A method is disclosed of fabricating a MIMCAP (a capacitor (CAP) formed by successive layers of metal, insulator, metal (MIM)) and a thin film resistor at the same level. A method is also disclosed of fabricating a MIMCAP and a thin film resistor at the same level, and a novel integration scheme for BEOL (back-end-of-line processing) thin film resistors which positions them closer to FEOL (front-end-of-line processing) devices.
    Type: Grant
    Filed: January 6, 2003
    Date of Patent: April 4, 2006
    Assignee: International Business Machines Corporation
    Inventors: Anil K. Chinthakindi, Shwu-Jen Jeng, Michael F. Lofaro, Christopher M. Schnabel, Kenneth J. Stein
  • Patent number: 7012499
    Abstract: A thin film resistor that has a substantially zero TCR is provided as well as a method for fabricating the same. The thin film resistor includes at least two resistor materials located over one another. Each resistor material has a different temperature coefficient of resistivity such that the effective temperature coefficient of resistivity of the thin film resistor is substantially 0 ppm/° C. The thin film resistor may be integrated into a interconnect structure or it may be integrated with a metal-insulator-metal capacitor (MIMCAP).
    Type: Grant
    Filed: June 2, 2003
    Date of Patent: March 14, 2006
    Assignee: International Business Machines Corporation
    Inventors: Jeffrey R. Amadon, Anil K. Chinthakindi, Kenneth J. Stein, Kwong H. Wong
  • Patent number: 6992368
    Abstract: Metal-insulator-metal capacitor structures are formed in semiconductor substrates using an anodization procedure on deposited underlying metalization followed by deposition of the second metal and planarization by chemical-mechanical polishing or other procedures. The process is additive in character, as opposed to traditional subtractive etch processes for forming capacitor structures. In addition, the process can be used in damascene applications, and can be used to form a wide variety of capacitive structures while reducing the number of mask layers required for formation.
    Type: Grant
    Filed: April 25, 2003
    Date of Patent: January 31, 2006
    Assignee: International Business Machines Corporation
    Inventors: Richard P. Volant, John M. Cotte, Kevin S. Petrarca, Kenneth J. Stein