Abstract: Methods and apparatus to decode dual-tone signals are disclosed. An example receiver to decode a dual-tone signal includes a tone detector to detect a start of a first tone, a first counter to count first cycles of the first tone, a second counter to count second cycles of a system clock while the first counter is counting and the first count is less than a first threshold, state control logic to start the second counter counting third cycles of the clock when a time period elapses, the third count being substantially equal to the second count, the first counter to count fourth cycles of a second tone while the third cycles are counted, and a decoder to compare the fourth count to a second threshold to identify an event represented by the signal.

Abstract: A light-emitting diode control circuit is provided, that includes: a duration selection circuit for selecting one of a first duration value, a second duration value, a third duration value, or a fourth duration value as a selected duration value based on a selection signal; a control clock generator for generating a control clock signal based on a slow clock signal and the selected duration value; a selection signal generator for generating the selection signal based on the control clock signal; an intensity signal generator for generating a current intensity signal based on a first intensity value, a second intensity value, the control clock signal, and the selection signal; a reference wave generator for generating a reference wave based on a fast clock signal; and a comparator for comparing the current intensity signal and the reference wave to generate a pulse width modulation signal to control the light-emitting diode.

Abstract: Methods and apparatus to decode dual-tone signals are disclosed. An example receiver to decode a dual-tone signal includes a tone detector to detect a start of a first tone, a first counter to count first cycles of the first tone, a second counter to count second cycles of a system clock while the first counter is counting and the first count is less than a first threshold, state control logic to start the second counter counting third cycles of the clock when a time period elapses, the third count being substantially equal to the second count, the first counter to count fourth cycles of a second tone while the third cycles are counted, and a decoder to compare the fourth count to a second threshold to identify an event represented by the signal.

Abstract: A light-emitting diode control circuit is provided, that includes: a duration selection circuit for selecting one of a first duration value, a second duration value, a third duration value, or a fourth duration value as a selected duration value based on a selection signal; a control clock generator for generating a control clock signal based on a slow clock signal and the selected duration value; a selection signal generator for generating the selection signal based on the control clock signal; an intensity signal generator for generating a current intensity signal based on a first intensity value, a second intensity value, the control clock signal, and the selection signal; a reference wave generator for generating a reference wave based on a fast clock signal; and a comparator for comparing the current intensity signal and the reference wave to generate a pulse width modulation signal to control the light-emitting diode.

Abstract: Linking addressable shadow port (LASP) and protocol allows addressing the LASP and configuring the connection of multiple Secondary Test Access Ports (TAPs) of the LASP using a single protocol or protocol bypass inputs. Multiple LASPs are cascaded and the connection of their secondary TAPs are configured using the LASP protocol or protocol bypass inputs.

Abstract: Linking addressable shadow port (LASP) and protocol allows addressing the LASP and configuring the connection of multiple Secondary Test Access Ports (TAPs) of the LASP using a single protocol or protocol bypass inputs. Multiple LASPs are cascaded and the connection of their secondary TAPs are configured using the LASP protocol or protocol bypass inputs.

Abstract: Linking addressable shadow port (LASP) and protocol allows addressing the LASP and configuring the connection of multiple Secondary Test Access Ports (TAPs) of the LASP using a single protocol or protocol bypass inputs. Multiple LASP are cascaded and the connection of their secondary TAPs are configured using the LASP protocol or protocol bypass inputs.

Abstract: Linking addressable shadow port (LASP) and protocol allows addressing the LASP and configuring the connection of multiple Secondary Test Access Ports (TAPs) of the LASP using a single protocol or protocol bypass inputs. Multiple LASP are cascaded and the connection of their secondary TAPs are configured using the LASP protocol or protocol bypass inputs.

Abstract: An asynchronous First-In-First-Out memory integrated circuit is equipped with a Built-In Self Test logic structure which allows extensive full-frequency asynchronous memory testing requiring minimal external test equipment. Memory input data patterns are generated by write data pattern circuitry responsive to a write clock signal. The write data generator considers the full status of the FIFO memory device. A read data generator provides an expected output data pattern corresponding to the data pattern provided by the write data generator responsive to a read clock signal such that the status of the FIFO memory device is taken into account. A read data error circuit compares the expected output data with the actual output data, indicating any mismatch between the two. Further this asynchronous First-In-First-Out memory device stores information regarding the nature of any mismatches and allows this information to be serially read from its output.

Abstract: An asynchronous First-In-First-Out memory integrated circuit is equipped with a Built-In Self Test logic structure which allows extensive full-frequency asynchronous memory testing requiring minimal external test equipment. Memory input data patterns are generated by write data pattern circuitry responsive to a write clock signal. The write data generator considers the full status of the FIFO memory device. A read data generator provides an expected output data pattern corresponding to the data pattern provided by the write data generator responsive to a read clock signal such that the status of the FIFO memory device is taken into account. A read data error circuit compares the expected output data with the actual output data, indicating any mismatch between the two. Further this asynchronous First-In-First-Out memory device stores information regarding the nature of any mismatches and allows this information to be serially read from its output.

Abstract: A fast FIFO memory system stores identical data in both static RAM memory and FIFO memory. Data is transferred from the FIFO when insufficient RAM read time is available. When the FIFO is full, additional data is stored in the RAM which runs at a much slower speed than the FIFO. Data is then transferred from the RAM until the FIFO is no longer full, at which time the memory system again functions at the faster FIFO speed.

Abstract: A reprogrammable FIFO status flags system for determining the status of a FIFO memory having a storage capacity (depth) D generates a pair of FIFO status flags, PAF (Programmable Almost Full) and PAE (Programmable Almost Empty) that can be reprogrammed multiple times, even after FIFO writes and reads have occurred. Two offset values (‘N’ and ‘M’) are programmed into the FIFO. PAE is high only when the number of words stored in the FIFO equals N or fewer. PAF is high only when the number of words stored in the FIFO equals D minus M or more.

Abstract: A microprocessor 1 is described which includes a direct memory access (DMA) circuitry 143. DMA 143 is interconnected with a program memory 23 and a data memory 22 and is operational to transfer data to or from these memories. DMA 143 is interconnected with a peripheral bus 110 and thereby to various peripherals internal to microprocessor 1. DMA 143 is also interconnected with an external memory interface 103 and thereby to various external memory circuits and peripherals external to microprocessor 1. An auxiliary channel control circuitry 160 provides DMA transfers by interacting with a peripheral such as host port 150 which has its own address generation circuitry. DMA 143 provides frame synchronization for triggering a frame transfer, or group of transfers. DMA 143 is auto-initialized through registers. DMA action complete pins DMAC0-3 indicate DMA status to external devices.

Abstract: A microprocessor 1 is described which includes a direct memory access (DMA) circuitry 143. DMA 143 is interconnected with a program memory 23 and a data memory 22 and is operational to transfer data to or from these memories. DMA 143 is interconnected with a peripheral bus 110 and thereby to various peripherals internal to microprocessor 1. DMA 143 is also interconnected with an external memory interface 103 and thereby to various external memory circuits and peripherals external to microprocessor 1. An auxiliary channel control circuitry 160 provides DMA transfers by interacting with a peripheral such as host port 150 which has its own address generation circuitry. DMA 143 provides frame synchronization for triggering a frame transfer, or group of transfers. DMA 143 is auto-initialized through registers. DMA action complete pins DMAC0-3 indicate DMA status to external devices.

Abstract: A sequential memory (10) uses interleaved memories (12a-b) with associated output buffers (22a-b) to accomplish high data rates. Data access control circuitry (18) and bank select circuitry (20) control the order in which the memory banks (12a-b) are written to and read from. Output buffer circuits (22a-b) allow a data word to be read instantaneously after it is written to the sequential memory (10).

Abstract: A clocked first-in first-out (FIFO) memory includes interleaved dual-port static random access memories (SRAM's) 32 and 36. The FIFO has status flags 44 to indicate empty and full conditions and two programmable flags, almost full and almost empty, to indicate when a selected number of words is stored in memory. In accordance with the present invention, the FIFO has retransmit capability, allowing previously read data to be accessed again. The FIFO is put in retransmit mode by providing a retransmit mode (RTM) input signal. This event causes the current read address stored in the read address registers 52 and 54, the interleave status in toggle circuit 22, the data in the data output latches 18 and 20 and in the pipeline latch 42, and the status flags 44, to be saved in shadow registers 64, 66, 24, (30, 62, 70, 116 and 120.

Abstract: A sequential memory (10) includes synchronous write control circuitry (26) and synchronous read control circuitry (22). The synchronous write control circuitry produces an Input Ready (IR) signal synchronous with the WRTCLK signal. The synchronous read control circuitry (22) generates a Output Ready (OR) signal synchronously with the RDCLK signal. A RSAM (read sense amplifier) signal is provided to read the sense amplifier associated with a memory (12) responsive to the RDCLK if a RAMRDY signal indicates that a read from this location may be requested on the next clock cycle.

Abstract: A sequential memory (10) uses interleaved memories (12a-b) with associated output buffers (22a-b) accomplish high data rates. Data access control circuitry (18) and bank select circuitry (20) control the order in which the memory banks (12a-b) are written to and read from. Output buffer circuits (22a-b) allow a data word to be read instantaneously after it is written to the sequential memory (10).

Abstract: A first-in, first-out memory (10) can store a programmable number of data words at respective address locations within a memory (76). A read address generator (50, 58) generates a read pointer for pointing to a read address location in the memory (76). A depth address generator (42) points to a depth address location in the memory that is displaced from the read address location by a predetermined number of address locations. This depth address generator (42) is incremented to a next read depth address responsive to a read pulse (20) issued from a read/write controller (12). A write address generator (80) points to a write address location within memory (76). A comparator (52) compares the value stored in the write address generator (42) to the read depth address location stored in depth address generator (42) and is operable to generate a FULL memory status flag (24) responsive to their equality.

Abstract: A FIFO 12 has a status flag generator 14. The status flag generator 14 includes a register programmable to "N". It also includes two sets of gray-code counters and a register (22,23,21;26,25,24) that are driven by separate READ and WRITE CLKS. The registers and counters are connected to comparators (31-36) for generating a plurality of signals that are input to output latches (41-43). The status flag generator is capable of generating status signals of FULL, HALF-FULL, EMPTY, FULL-N and EMPTY+N. N is a user-defined number that is programmed into a register 20 that is selectively connected to one or more of the programmable gray-code counters (23,24).