Abstract: A first-in, first-out memory has a write pointer (34) that includes a higher-order ring counter (192) and a lower-order ring counter (190). Ring counters (190, 192) store respective higher-order and lower-order address digits that are together used to select one of a plurality of write select gates (202). Each gate (202) is operable to both power up and address is coupled to a respective memory word location. A read pointer (28) of the FIFO has an analogous architecture. The lower-order and higher-order address digits generated by the write and read pointers (34 and 28) are used by a pointer comparator (44) to generate a plurality of intermediate signals. The intermediate signals are in turn received by a flag decoder (52) that generates EMPTY, FULL, ALMOST-FULL/EMPTY, and HALF-FULL status flags. A write-read control section (48) of the FIFO has a pair of monostable multivibrators (68, 82) that generate write and read clock pulses of a uniform pulse width.

Abstract: A cascadable first-in, first-out memory unit (11, 12, 13) has a load/unload control (152) for write-addressing and read-addressing selected memory locations within its memory array (82). A write pointer (110, 112, 120) keeps track of the number of write operations that have occurred in the selected memory unit, and a read pointer (130, 132, 142) does the same for the number of read operations. When the number of write operations performed since a last reset pulse (416) equals the number of memory locations in the memory array (82), write control passes to the next succeeding FIFO memory unit by a descending transition of an output control signal (444). Read control is passed to the subsequent FIFO by an ascending transition (470) of the same output control signal.

Abstract: A First-In First-Out (FIFO) shift register memory system (10) with a plurality of memory word registers (50) having data inputs connected to a common data-in bus (16), and a plurality of data outputs connected to a common data-out bus (22). A write address ring counter (32) is responsive to first transitions (164, 168) of a write pulses to increment to successive stages (32) therein. A plurality of latches (154) are each responsive to a second transition (166) to latch in a write address bit. The latches (154) are each enabled to write the address bit to a respective memory register (50) upon a successive first transition (168).

Abstract: A portable, self-contained precision concentricity gauge having a workpiece support portion and gauge support portion mounted on a unitary base plate. The workpiece support portion uses a pair of driven rollers and a moveable idler roller to rotationally support a workpiece. The gauge support portion comprises a gauge carrier which rides on a carrier shaft cantilevered out from the workpiece support portion and adapted for three directions of motion relative to the workpiece. A guide shaft, parallel to the carrier shaft, cooperates with a magnet on the gauge carrier for permitting rotation of the gauge carrier and probe for replacing the workpiece without disturbing the position adjustment of the probe.

Abstract: A brake valve is disclosed, which is provided with an enlarged chamber, at one end of which is slidably disposed an annular piston. A reaction piston is carried on a valve rod; the reaction piston radially extends so as to cover the annular piston. When the reaction piston moves toward the annular piston, flow of fluid through the valve is restricted and then halted. Mating beveled conical surfaces are provided on the annular piston and the reaction piston to provide a mutual centering and seating action as the reaction piston is moved toward the annular piston. Belleville washer elements are stacked in opposed array on the valve rod for resiliently urging the reaction piston into engagement with the annular piston, and for inhibiting mechanical shocks from being transmitted from the valve rod to the reaction piston, and vice versa. Conical fluid flow stop members regulate the flow of fluid from the valve chamber to downstream brake elements.