Patents by Inventor Kenneth L. Wright

Kenneth L. Wright has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 11705187
    Abstract: Described are memory modules that support different error detection and correction (EDC) schemes in both single- and multiple-module memory systems. The memory modules are width configurable and support the different EDC schemes for relatively wide and narrow module data widths. Data buffers on the modules support the half-width and full-width modes, and also support time-division-multiplexing to access additional memory components on each module in support of enhanced EDC.
    Type: Grant
    Filed: October 14, 2021
    Date of Patent: July 18, 2023
    Assignee: Rambus Inc.
    Inventors: Frederick A. Ware, John Eric Linstadt, Kenneth L. Wright
  • Patent number: 11625346
    Abstract: Memory controllers, devices, modules, systems and associated methods are disclosed. In one embodiment, an integrated circuit (IC) memory component is disclosed that includes a memory core, a primary interface, and a secondary interface. The primary interface includes data input/output (I/O) circuitry and control/address (C/A) input circuitry, and accesses the memory core during a normal mode of operation. The secondary interface accesses the memory core during a fault mode of operation.
    Type: Grant
    Filed: April 7, 2022
    Date of Patent: April 11, 2023
    Assignee: Rambus Inc.
    Inventors: Frederick A. Ware, Kenneth L. Wright
  • Publication number: 20220406354
    Abstract: A memory module includes cache of relatively fast and durable dynamic, random-access memory (DRAM) in service of a larger amount of relatively slow and wear-sensitive nonvolatile memory. Local controller manages communication between the DRAM cache and nonvolatile memory to accommodate disparate access granularities, reduce the requisite number of memory transactions, and minimize the flow of data external to nonvolatile memory components.
    Type: Application
    Filed: June 28, 2022
    Publication date: December 22, 2022
    Inventors: Frederick A. Ware, John Eric Linstadt, Kenneth L. Wright
  • Publication number: 20220350763
    Abstract: The embodiments described herein describe technologies of dynamic random access memory (DRAM) components for high-performance, high-capacity registered memory modules, such as registered dual in-line memory modules (RDIMMs). One DRAM component may include a set of memory cells and steering logic. The steering logic may include a first data interface and a second data interface. The first and second data interfaces are selectively coupled to a controller component in a first mode and the first data interface is selectively coupled to the controller component in a second mode and the second data interface is selectively coupled to a second DRAM component in the second mode.
    Type: Application
    Filed: May 19, 2022
    Publication date: November 3, 2022
    Inventors: Frederick A. Ware, Ely Tsern, John Eric Linstadt, Thomas J. Giovannini, Kenneth L. Wright
  • Patent number: 11456025
    Abstract: A memory module includes cache of relatively fast and durable dynamic, random-access memory (DRAM) in service of a larger amount of relatively slow and wear-sensitive nonvolatile memory. Local controller manages communication between the DRAM cache and nonvolatile memory to accommodate disparate access granularities, reduce the requisite number of memory transactions, and minimize the flow of data external to nonvolatile memory components.
    Type: Grant
    Filed: November 5, 2020
    Date of Patent: September 27, 2022
    Assignee: Rambus Inc.
    Inventors: Frederick A. Ware, John Eric Linstadt, Kenneth L. Wright
  • Publication number: 20220300439
    Abstract: Memory controllers, devices, modules, systems and associated methods are disclosed. In one embodiment, an integrated circuit (IC) memory component is disclosed that includes a memory core, a primary interface, and a secondary interface. The primary interface includes data input/output (I/O) circuitry and control/address (C/A) input circuitry, and accesses the memory core during a normal mode of operation. The secondary interface accesses the memory core during a fault mode of operation.
    Type: Application
    Filed: April 7, 2022
    Publication date: September 22, 2022
    Inventors: Frederick A. Ware, Kenneth L. Wright
  • Patent number: 11373176
    Abstract: A computer-implemented method includes receiving, by a federated identity computing system, identity information from a customer; receiving, by the computing system, preferences for the identity information from the customer, wherein the preferences govern distribution of the identity information to requesting parties; generating, by the computing system, a key specific to the customer; and provisioning, by the computing system, the key to an identification chip associated with the customer. The computer-implemented method further includes receiving, by the computing system, the key and a request for one or more pieces of the identity information from a requesting party and providing, by the computing system, the requested one or more pieces of identity information to the requesting party based on the key and the preferences.
    Type: Grant
    Filed: February 22, 2018
    Date of Patent: June 28, 2022
    Assignee: Wells Fargo Bank, N.A.
    Inventors: Jana L. Chilton, Angira Goswami, Muhammad Farukh Munir, Traci Nguyen, Priyamvada Singh, Darrell L. Suen, Kenneth L. Wright
  • Publication number: 20220171721
    Abstract: Memory controllers, devices, modules, systems and associated methods are disclosed. In one embodiment, a memory module includes a pin interface for coupling to a bus. The bus has a first width. The module includes at least one storage class memory (SCM) component and at least one DRAM component. The memory module operates in a first mode that utilizes all of the first width, and in a second mode that utilizes less than all of the first width.
    Type: Application
    Filed: December 11, 2021
    Publication date: June 2, 2022
    Inventors: Frederick A. Ware, Kenneth L. Wright, John Eric Linstadt, Craig Hampel
  • Patent number: 11341070
    Abstract: The embodiments described herein describe technologies of dynamic random access memory (DRAM) components for high-performance, high-capacity registered memory modules, such as registered dual in-line memory modules (RDIMMs). One DRAM component may include a set of memory cells and steering logic. The steering logic may include a first data interface and a second data interface. The first and second data interfaces are selectively coupled to a controller component in a first mode and the first data interface is selectively coupled to the controller component in a second mode and the second data interface is selectively coupled to a second DRAM component in the second mode.
    Type: Grant
    Filed: November 20, 2020
    Date of Patent: May 24, 2022
    Assignee: Rambus, Inc.
    Inventors: Frederick A. Ware, Ely Tsern, John Eric Linstadt, Thomas J. Giovannini, Kenneth L. Wright
  • Publication number: 20220148643
    Abstract: A memory system includes dynamic random-access memory (DRAM) components that include interconnected and redundant component data interfaces. The redundant interfaces facilitate memory interconnect topologies that accommodate considerably more DRAM components per memory channel than do traditional memory systems, and thus offer considerably more memory capacity per channel, without concomitant reductions in signaling speeds. Each DRAM component includes multiplexers that allow either of the data interfaces to write data to or read data from a common set of memory banks, and to selectively relay write and read data to and from other components, bypassing the local banks. Delay elements can impose selected read/write delays to align read and write transactions from and to disparate DRAM components.
    Type: Application
    Filed: November 22, 2021
    Publication date: May 12, 2022
    Inventors: Frederick A. Ware, Ely K. Tsern, John E. Linstadt, Thomas A. Giovannini, Scott C. Best, Kenneth L. Wright
  • Patent number: 11308009
    Abstract: Memory controllers, devices, modules, systems and associated methods are disclosed. In one embodiment, an integrated circuit (IC) memory component is disclosed that includes a memory core, a primary interface, and a secondary interface. The primary interface includes data input/output (I/O) circuitry and control/address (C/A) input circuitry, and accesses the memory core during a normal mode of operation. The secondary interface accesses the memory core during a fault mode of operation.
    Type: Grant
    Filed: August 22, 2019
    Date of Patent: April 19, 2022
    Assignee: Rambus Inc.
    Inventors: Frederick A. Ware, Kenneth L. Wright
  • Publication number: 20220101912
    Abstract: Described are memory modules that support different error detection and correction (EDC) schemes in both single- and multiple-module memory systems. The memory modules are width configurable and support the different EDC schemes for relatively wide and narrow module data widths. Data buffers on the modules support the half-width and full-width modes, and also support time-division-multiplexing to access additional memory components on each module in support of enhanced EDC.
    Type: Application
    Filed: October 14, 2021
    Publication date: March 31, 2022
    Inventors: Frederick A. Ware, John Eric Linstadt, Kenneth L. Wright
  • Patent number: 11264085
    Abstract: In a memory component having a page buffer with 2N independently accessible regions, N bits of a command/address value are decoded to access contents within a first one of the 2N page-buffer regions if a configuration value specifies a first addressing resolution and, if the configuration value specifies a second addressing resolution, a composite address that includes fewer than N bits of the command/address value together with a plurality of bits generated within the memory component to access contents within a second one of the 2N page-buffer regions.
    Type: Grant
    Filed: July 13, 2020
    Date of Patent: March 1, 2022
    Assignee: Rambus Inc.
    Inventors: Frederick A. Ware, John Eric Linstadt, Kenneth L. Wright
  • Publication number: 20220005519
    Abstract: A memory component includes a first memory bank. The first memory bank has a plurality of sub-arrays having sub-rows of memory elements. The memory component includes a write driver, coupled to the first memory bank, to perform a write operation of an entire sub-row of a sub-array. To perform the write operation, the write driver is to load a burst of write data to the memory bank. The memory bank may then activate a plurality of sense amplifiers associated with a plurality of memory elements of the entire sub-row to load the burst of write data to the plurality of sense amplifiers.
    Type: Application
    Filed: July 14, 2021
    Publication date: January 6, 2022
    Inventors: Frederick A. Ware, John Eric Linstadt, Brent Steven Haukness, Kenneth L. Wright, Thomas Vogelsang
  • Patent number: 11210242
    Abstract: Memory controllers, devices, modules, systems and associated methods are disclosed. In one embodiment, a memory module includes a pin interface for coupling to a bus. The bus has a first width. The module includes at least one storage class memory (SCM) component and at least one DRAM component. The memory module operates in a first mode that utilizes all of the first width, and in a second mode that utilizes less than all of the first width.
    Type: Grant
    Filed: May 29, 2020
    Date of Patent: December 28, 2021
    Assignee: Rambus Inc.
    Inventors: Frederick A. Ware, Kenneth L. Wright, John Eric Linstadt, Craig Hampel
  • Patent number: 11211114
    Abstract: A memory system includes dynamic random-access memory (DRAM) components that include interconnected and redundant component data interfaces. The redundant interfaces facilitate memory interconnect topologies that accommodate considerably more DRAM components per memory channel than do traditional memory systems, and thus offer considerably more memory capacity per channel, without concomitant reductions in signaling speeds. Each DRAM component includes multiplexers that allow either of the data interfaces to write data to or read data from a common set of memory banks, and to selectively relay write and read data to and from other components, bypassing the local banks. Delay elements can impose selected read/write delays to align read and write transactions from and to disparate DRAM components.
    Type: Grant
    Filed: July 3, 2019
    Date of Patent: December 28, 2021
    Assignee: Rambus Inc.
    Inventors: Frederick A. Ware, Ely K. Tsern, John E. Linstadt, Thomas J. Giovannini, Scott C. Best, Kenneth L. Wright
  • Publication number: 20210374004
    Abstract: A memory system includes dynamic random-access memory (DRAM) components that include interconnected and redundant component data interfaces. The redundant interfaces facilitate memory interconnect topologies that accommodate considerably more DRAM components per memory channel than do traditional memory systems, and thus offer considerably more memory capacity per channel, without concomitant reductions in signaling speeds. The memory components can be configured to route data around defective data connections to maintain full capacity and continue to support memory transactions.
    Type: Application
    Filed: June 22, 2021
    Publication date: December 2, 2021
    Inventors: Kenneth L. Wright, Frederick A. Ware
  • Patent number: 11164622
    Abstract: Described are memory modules that support different error detection and correction (EDC) schemes in both single- and multiple-module memory systems. The memory modules are width configurable and support the different EDC schemes for relatively wide and narrow module data widths. Data buffers on the modules support the half-width and full-width modes, and also support time-division-multiplexing to access additional memory components on each module in support of enhanced EDC.
    Type: Grant
    Filed: November 23, 2020
    Date of Patent: November 2, 2021
    Assignee: Rambus Inc.
    Inventors: Frederick A. Ware, John Eric Linstadt, Kenneth L. Wright
  • Patent number: 11132425
    Abstract: Systems, methods, and apparatuses for authenticating a user based at least in part on a location of the user or a location of a user device are described. The user may be authenticated as part of a financial transaction or as part of a login process for a computing device. The user device was previously bound or associated with the user. During the authentication, a system (e.g., a financial institution computing system or a backend authentication system) requests location information from the user device. The location information may be packaged as a digital fingerprint of the user device, which can only be created from the user device. Based on the location information, the user can be authenticated thereby approving the transaction or login request.
    Type: Grant
    Filed: July 7, 2016
    Date of Patent: September 28, 2021
    Assignee: Wells Fargo Bank, N.A.
    Inventors: Gerard K. Cohen, Michelle D. Green, Christopher P. Smith, Craig Stuart, Kenneth L. Wright, Michelle M. Young
  • Patent number: 11069392
    Abstract: A memory component includes a first memory bank. The first memory bank has a plurality of sub-arrays having sub-rows of memory elements. The memory component includes a write driver, coupled to the first memory bank, to perform a write operation of an entire sub-row of a sub-array. To perform the write operation, the write driver is to load a burst of write data to the memory bank. The memory bank may then activate a plurality of sense amplifiers associated with a plurality of memory elements of the entire sub-row to load the burst of write data to the plurality of sense amplifiers.
    Type: Grant
    Filed: November 16, 2020
    Date of Patent: July 20, 2021
    Assignee: Rambus, Inc.
    Inventors: Frederick A. Ware, John Eric Linstadt, Brent Steven Haukness, Kenneth L. Wright, Thomas Vogelsang