Abstract: Memory controllers, devices, modules, systems and associated methods are disclosed. In one embodiment, an integrated circuit (IC) memory component is disclosed that includes a memory core, a primary interface, and a secondary interface. The primary interface includes data input/output (I/O) circuitry and control/address (C/A) input circuitry, and accesses the memory core during a normal mode of operation. The secondary interface accesses the memory core during a fault mode of operation.

Abstract: A memory system includes dynamic random-access memory (DRAM) components that include interconnected and redundant component data interfaces. The redundant interfaces facilitate memory interconnect topologies that accommodate considerably more DRAM components per memory channel than do traditional memory systems, and thus offer considerably more memory capacity per channel, without concomitant reductions in signaling speeds. The memory components can be configured to route data around defective data connections to maintain full capacity and continue to support memory transactions.

Abstract: A memory controller may receive a plurality of thermal profiles from a plurality of three-dimensional (3D)-stacked memory chips, where the plurality of thermal profiles include thermal profile data for the memory chips, where the thermal profile data includes a memory chip usage data and a location data for each of the memory chips, and where the memory chips include a first memory chip and a second memory chip. The memory controller may generate a first predicted memory chip usage data and location data by analyzing the usage data and location data of the thermal profile data. A second predicted memory chip usage data and location data may be generated. Based on the predicted memory chip, fractional memory chip read propensity data may be generated. The memory controller may distribute, according the first fractional memory chip read propensity distribution, memory chip read operations.

Abstract: A memory controller may receive a plurality of thermal profiles from a plurality of three-dimensional (3D)-stacked memory chips, where the plurality of thermal profiles include thermal profile data for the memory chips, where the thermal profile data includes a memory chip usage data and a location data for each of the memory chips, and where the memory chips include a first memory chip and a second memory chip. The memory controller may generate a first predicted memory chip usage data and location data by analyzing the usage data and location data of the thermal profile data. A second predicted memory chip usage data and location data may be generated. Based on the predicted memory chip, fractional memory chip read propensity data may be generated. The memory controller may distribute, according the first fractional memory chip read propensity distribution, memory chip read operations.

Abstract: A method, system, and computer program product for system-wide power conservation using memory cache are provided. A memory access request is received at a location in a memory architecture where processing the memory access request has to use a last level of cache before reaching a memory device holding a requested data. Using a memory controller, the memory access request is caused to wait, omitting adding the memory access request to a queue of existing memory access requests accepted for processing using the last level of cache. All the existing memory access requests in the queue are processed using the last level of cache. The last level of cache is purged to the memory device. The memory access request is processed using an alternative path to the memory device that avoids the last level of cache. A cache device used as the last level of cache is powered down.

Abstract: A system provides complex branch execution hardware and a hardware-based Multiplexer (MUX) to multiplex a fetch address of a future branch and a preloaded branch fetch address to create an index hash value that is used to index a branch target prediction table for execution by a processor core, in order to reduce branch mis-prediction by preloading.

Abstract: A memory controller is equipped with multiple error correction circuits for different complexity levels of errors, but requested data is initially sent to a requesting unit (e.g., processor) via a bypass path which provides the lowest memory latency. The requesting unit performs error detection and, if an error is found, sends a retry select signal to the memory controller. The retry select signal provides an indication of which error correction unit should be used to provide complete correction of the error but add the minimum latency necessary. On the retry transmission, the controller uses the particular error correction unit indicated by the retry select signal. The memory controller can also have a persistent error detection circuit which identifies an address as being defective when an error is repeatedly indicated by multiple retry select signals, and the control logic can automatically transmits the requested data using the appropriate error correction unit.

Abstract: A memory controller is equipped with multiple error correction circuits for different complexity levels of errors, but requested data is initially sent to a requesting unit (e.g., processor) via a bypass path which provides the lowest memory latency. The requesting unit performs error detection and, if an error is found, sends a retry select signal to the memory controller. The retry select signal provides an indication of which error correction unit should be used to provide complete correction of the error but add the minimum latency necessary. On the retry transmission, the controller uses the particular error correction unit indicated by the retry select signal. The memory controller can also have a persistent error detection circuit which identifies an address as being defective when an error is repeatedly indicated by multiple retry select signals, and the control logic can automatically transmits the requested data using the appropriate error correction unit.

Abstract: A system for memory device control may include a stacked memory device and a memory controller. The stacked memory device may include a stack of chips connected to a package substrate by electrical interconnects. The stack may include a plurality of memory chips, a primary control chip, and a secondary control chip. The primary and secondary control chips may be electrically connected to the plurality of memory chips by an internal data bus. The primary control chip may have logic to provide an interface between the internal data bus and a first external data bus. The secondary control chip may have logic to provide an interface between the internal data bus and a second external data bus.

Abstract: A system for memory device control may include a stacked memory device and a memory controller. The stacked memory device may include a stack of chips connected to a package substrate by electrical interconnects. The stack may include a plurality of memory chips, a primary control chip, and a secondary control chip. The primary and secondary control chips may be electrically connected to the plurality of memory chips by an internal data bus. The primary control chip may have logic to provide an interface between the internal data bus and a first external data bus. The secondary control chip may have logic to provide an interface between the internal data bus and a second external data bus.

Abstract: Data is retrieved from a stacked memory device having a plurality of slave memory chips in response to recognizing a problem in the stacked memory device. The problem is determined to be associated with a primary driver module in the stacked memory device. In response, the primary driver module is disabled and an emergency driver module is enabled. Each of the plurality of slave memory chips are selected using a multiplexing unit to retrieve data using the emergency driver module.

Abstract: Data is retrieved from a stacked memory device having a plurality of slave memory chips in response to recognizing a problem in the stacked memory device. The problem is determined to be associated with a primary driver module in the stacked memory device. In response, the primary driver module is disabled and an emergency driver module is enabled. Each of the plurality of slave memory chips are selected using a multiplexing unit to retrieve data using the emergency driver module.

Abstract: A method for mirroring in three-dimensional-stacked memory includes receiving a plurality of thermal profiles from a plurality of memory chips. The method also includes ranking the plurality of memory chips in a first ranked list of memory chips as a function of the plurality of thermal profiles and forming a first group of memory chips from the plurality of memory chips based on the first ranked list of memory chips. The method also includes forming a second group of memory chips from the plurality of memory chips distinct from the first group of memory chips based on the first ranked list of memory chips. The method also includes pairing a first memory chip from the first group of memory chips and a second memory chip from the second group of memory chips, and mirroring the pairing of memory chips.

Abstract: The present disclosure includes a three dimensional (3D) integrated device comprising a first die having a first supply line and a second die having a second supply line, a power header, and voltage selection logic. The power header is connected to the first die and the second die and configured to generate a first voltage on a first voltage line and a second voltage on a second voltage line. The voltage selection logic is connected to the first supply line and the second supply line and configured to select between the first voltage line and the second voltage line for each of the first supply line and the second supply line.

Abstract: A method for mirroring in three-dimensional-stacked memory includes receiving a plurality of thermal profiles from a plurality of memory chips. The method also includes ranking the plurality of memory chips in a first ranked list of memory chips as a function of the plurality of thermal profiles and forming a first group of memory chips from the plurality of memory chips based on the first ranked list of memory chips. The method also includes forming a second group of memory chips from the plurality of memory chips distinct from the first group of memory chips based on the first ranked list of memory chips. The method also includes pairing a first memory chip from the first group of memory chips and a second memory chip from the second group of memory chips, and mirroring the pairing of memory chips.

Abstract: A method for mirroring in three-dimensional-stacked memory includes receiving a plurality of thermal profiles from a plurality of memory chips. The method also includes ranking the plurality of memory chips in a first ranked list of memory chips as a function of the plurality of thermal profiles and forming a first group of memory chips from the plurality of memory chips based on the first ranked list of memory chips. The method also includes forming a second group of memory chips from the plurality of memory chips distinct from the first group of memory chips based on the first ranked list of memory chips. The method also includes pairing a first memory chip from the first group of memory chips and a second memory chip from the second group of memory chips, and mirroring the pairing of memory chips.

Abstract: A method for mirroring in three-dimensional-stacked memory includes receiving a plurality of thermal profiles from a plurality of memory chips. The method also includes ranking the plurality of memory chips in a first ranked list of memory chips as a function of the plurality of thermal profiles and forming a first group of memory chips from the plurality of memory chips based on the first ranked list of memory chips. The method also includes forming a second group of memory chips from the plurality of memory chips distinct from the first group of memory chips based on the first ranked list of memory chips. The method also includes pairing a first memory chip from the first group of memory chips and a second memory chip from the second group of memory chips, and mirroring the pairing of memory chips.

Abstract: An electronic system having a power efficient differential signal between a first and second electronic unit. A controller uses information, such as compliance with data transmission rate requirement and bit error rate (BER) versus a BER threshold to control power modes such that a minimal amount of power is required. Amplitude of transmission and single ended or differential transmission of data are examples of the power modes. The controller also factors in a failing phase in a differential signal in selecting a minimal power mode that satisfies the transmission rate requirement of the BER threshold.

Abstract: The present disclosure includes a three dimensional (3D) integrated device comprising a first die having a first supply line and a second die having a second supply line, a power header, and voltage selection logic. The power header is connected to the first die and the second die and configured to generate a first voltage on a first voltage line and a second voltage on a second voltage line. The voltage selection logic is connected to the first supply line and the second supply line and configured to select between the first voltage line and the second voltage line for each of the first supply line and the second supply line.

Abstract: A system for memory device control may include a stacked memory device and a memory controller. The stacked memory device may include a stack of chips connected to a package substrate by electrical interconnects. The stack may include a plurality of memory chips, a primary control chip, and a secondary control chip. The primary and secondary control chips may be electrically connected to the plurality of memory chips by an internal data bus. The primary control chip may have logic to provide an interface between the internal data bus and a first external data bus. The secondary control chip may have logic to provide an interface between the internal data bus and a second external data bus.