Patents by Inventor Kenneth Lee Wright

Kenneth Lee Wright has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20210035623
    Abstract: Memory devices, controllers and associated methods are disclosed. In one embodiment, a memory device is disclosed. The memory device includes storage cells that are each formed with a metal-oxide-semiconductor (MOS) transistor having a floating body. Data is stored as charge in the floating body. A transfer interface receives a read command to access data stored in a first group of the storage cells. Sensing circuitry detects the data stored in the first group of storage cells. The transfer interface selectively performs a writeback operation of the sensed data associated with the read command.
    Type: Application
    Filed: August 21, 2020
    Publication date: February 4, 2021
    Inventors: Frederick A. Ware, John Eric Linstadt, Zhichao Lu, Kenneth Lee Wright
  • Publication number: 20210004337
    Abstract: A memory module comprises an address buffer circuit, a command/address channel, and a plurality of memory components controlled by the address buffer circuit via the command/address channel. At least one memory component comprises a plurality of data ports, a memory core to store data, and a data interface. The data interface is capable of transferring data between the memory core and the data ports. The data interface supports a first data width mode in which the data interface transfers data at a first bit width and a first burst length via the data ports. The data interface also supports a second data width mode in which the data interface transfers data at a second bit width and second burst length via the data ports. The first bit width is greater than the second bit width and the first burst length is shorter than the second burst length.
    Type: Application
    Filed: July 29, 2020
    Publication date: January 7, 2021
    Inventors: Frederick A. Ware, John Eric Linstadt, Kenneth Lee Wright
  • Patent number: 10762010
    Abstract: A memory module comprises an address buffer circuit, a command/address channel, and a plurality of memory components controlled by the address buffer circuit via the command/address channel. At least one memory component comprises a plurality of data ports, a memory core to store data, and a data interface. The data interface is capable of transferring data between the memory core and the data ports. The data interface supports a first data width mode in which the data interface transfers data at a first bit width and a first burst length via the data ports. The data interface also supports a second data width mode in which the data interface transfers data at a second bit width and second burst length via the data ports. The first bit width is greater than the second bit width and the first burst length is shorter than the second burst length.
    Type: Grant
    Filed: November 9, 2017
    Date of Patent: September 1, 2020
    Assignee: Rambus Inc.
    Inventors: Frederick A. Ware, John Eric Linstadt, Kenneth Lee Wright
  • Patent number: 10762948
    Abstract: Memory devices, controllers and associated methods are provided. In one embodiment, a memory device is provided. The memory device includes storage cells that are each formed with a metal-oxide-semiconductor (MOS) transistor having a floating body. Data is stored as charge in the floating body. A transfer interface receives a read command to access data stored in a first group of the storage cells. Sensing circuitry detects the data stored in the first group of storage cells. The transfer interface selectively performs a writeback operation of the sensed data associated with the read command.
    Type: Grant
    Filed: December 1, 2017
    Date of Patent: September 1, 2020
    Assignee: Rambus Inc.
    Inventors: Frederick A. Ware, John Eric Linstadt, Zhichao Lu, Kenneth Lee Wright
  • Publication number: 20180166120
    Abstract: Memory devices, controllers and associated methods are disclosed. In one embodiment, a memory device is disclosed. The memory device includes storage cells that are each formed with a metal-oxide-semiconductor (MOS) transistor having a floating body. Data is stored as charge in the floating body. A transfer interface receives a read command to access data stored in a first group of the storage cells. Sensing circuitry detects the data stored in the first group of storage cells. The transfer interface selectively performs a writeback operation of the sensed data associated with the read command.
    Type: Application
    Filed: December 1, 2017
    Publication date: June 14, 2018
    Inventors: Frederick A. Ware, John Eric Linstadt, Zhichao Lu, Kenneth Lee Wright
  • Publication number: 20180137067
    Abstract: A memory module comprises an address buffer circuit, a command/address channel, and a plurality of memory components controlled by the address buffer circuit via the command/address channel. At least one memory component comprises a plurality of data ports, a memory core to store data, and a data interface. The data interface is capable of transferring data between the memory core and the data ports. The data interface supports a first data width mode in which the data interface transfers data at a first bit width and a first burst length via the data ports. The data interface also supports a second data width mode in which the data interface transfers data at a second bit width and second burst length via the data ports. The first bit width is greater than the second bit width and the first burst length is shorter than the second burst length.
    Type: Application
    Filed: November 9, 2017
    Publication date: May 17, 2018
    Inventors: Frederick A. Ware, John Eric Linstadt, Kenneth Lee Wright
  • Patent number: 7818364
    Abstract: A processor communication register (PCR) contained within a multiprocessor cluster system provides enhanced processor communication. The PCR stores information that is useful in pipelined or parallel multi-processing. Each processor cluster has exclusive rights to store to a sector within the PCR and has continuous access to read its contents. Each processor cluster updates its exclusive sector within the PCR, instantly allowing all of the other processors within the cluster network to see the change within the PCR data, and bypassing the cache subsystem. Efficiency is enhanced within the processor cluster network by providing processor communications to be immediately networked and transferred into all processors without momentarily restricting access to the information or forcing all the processors to be continually contending for the same cache line, and thereby overwhelming the interconnect and memory system with an endless stream of load, store and invalidate commands.
    Type: Grant
    Filed: December 7, 2007
    Date of Patent: October 19, 2010
    Assignee: International Business Machines Corporation
    Inventors: Ravi Kumar Arimilli, Robert Alan Cargnoni, Derek Edward Williams, Kenneth Lee Wright
  • Publication number: 20100162037
    Abstract: A memory system includes a memory controller, one or more memory channel(s), and a memory subsystem having a memory interface device (e.g. a hub or buffer device) located on a memory subsystem (e.g. a DIMM) coupled to the memory channel to communicate with the memory device(s) array. This buffered DIMM is provided with one or more spare chips on the DIMM, wherein the data bits sourced from the spare chips are connected to the memory hub device and the bus to the DIMM includes only those data bits used for normal operation. The buffered DIMM with one or more spare chips on the DIMM has the spare memory shared among all the ranks, and the memory hub device includes separate control bus(es) for the spare memory device to allow the spare memory device(s) to be utilized to replace one or more failing bits and/or devices within any rank of memory in the memory subsystem.
    Type: Application
    Filed: December 22, 2008
    Publication date: June 24, 2010
    Applicant: International Business Machines Corporation
    Inventors: Warren Edward Maule, Kevin C. Gower, Kenneth Lee Wright
  • Patent number: 7734877
    Abstract: A processor communication register (PCR) contained in each processor within a multiprocessor cluster network provides enhanced processor communication. Each PCR stores identical processor communication information that is useful in pipelined or parallel multi-processing. Each processor has exclusive rights to store to a sector within each PCR within the cluster network and has continuous access to read the contents of its own PCR. Each processor updates its exclusive sector within all of the PCRs via a private protocol or dedicated wireless network, instantly allowing all of the other processors within the cluster network to see the change within the PCR data, and bypassing the cache subsystem.
    Type: Grant
    Filed: December 12, 2007
    Date of Patent: June 8, 2010
    Assignee: International Business Machines Corporation
    Inventors: Ravi Kumar Arimilli, Robert Alan Cargnoni, Derek Edward Williams, Kenneth Lee Wright
  • Patent number: 7698373
    Abstract: A processor communication register (PCR) contained in each processor within a multiprocessor system provides enhanced processor communication. Each PCR stores identical processor communication information that is useful in pipelined or parallel multi-processing. Each processor has exclusive rights to store to a sector within each PCR and has continuous access to read the contents of its own PCR. Each processor updates its exclusive sector within all of the PCRs, instantly allowing all of the other processors to see the change within the PCR data, and bypassing the cache subsystem. Efficiency is enhanced within the multiprocessor system by providing processor communications to be immediately transferred into all processors without momentarily restricting access to the information or forcing all the processors to be continually contending for the same cache line, and thereby overwhelming the interconnect and memory system with an endless stream of load, store and invalidate commands.
    Type: Grant
    Filed: January 10, 2008
    Date of Patent: April 13, 2010
    Assignee: International Business Machines Corporation
    Inventors: Ravi Kumar Arimilli, Robert Alan Cargnoni, Derek Edward Williams, Kenneth Lee Wright
  • Patent number: 7493417
    Abstract: Processor communication registers (PCRs) contained in each processor within a multiprocessor system and interconnected by a specialized bus provides enhanced processor communication. Each PCR stores identical processor communication information that is useful in pipelined or parallel multi-processing. Each processor has exclusive rights to store to a sector within each PCR and has continuous access to read the contents of its own PCR. Each processor updates its exclusive sector within all of the PCRs utilizing communication over the specialized bus, instantly allowing all of the other processors to see the change within the PCR data, and bypassing the cache subsystem.
    Type: Grant
    Filed: December 12, 2002
    Date of Patent: February 17, 2009
    Assignee: International Business Machines Corporation
    Inventors: Ravi Kumar Arimilli, Robert Alan Cargnoni, Derek Edward Williams, Kenneth Lee Wright
  • Patent number: 7409504
    Abstract: A method for sequentially coupling successive processor requests for a cache line before the data is received in the cache of a first coupled processor. Both homogenous and non-homogenous operations are chained to each other, and the coherency protocol includes several new intermediate coherency responses associated with the chained states. Chained coherency states are assigned to track the chain of processor requests and the grant of access permission prior to receipt of the data at the first processor. The chained coherency states also identify the address of the receiving processor. When data is received at the cache of the first processor within the chain, the processor completes its operation on (or with) the data and then forwards the data to the next processor in the chain. The chained coherency protocol frees up address bus bandwidth by reducing the number of retries.
    Type: Grant
    Filed: October 6, 2005
    Date of Patent: August 5, 2008
    Assignee: International Business Machines Corporation
    Inventors: Ramakrishnan Rajamony, Hazim Shafi, Derek Edward Williams, Kenneth Lee Wright
  • Publication number: 20080155231
    Abstract: A processor communication register (PCR) contained in each processor within a multiprocessor cluster network provides enhanced processor communication. Each PCR stores identical processor communication information that is useful in pipelined or parallel multi-processing. Each processor has exclusive rights to store to a sector within each PCR within the cluster network and has continuous access to read the contents of its own PCR. Each processor updates its exclusive sector within all of the PCRs via a private protocol or dedicated wireless network, instantly allowing all of the other processors within the cluster network to see the change within the PCR data, and bypassing the cache subsystem.
    Type: Application
    Filed: December 12, 2007
    Publication date: June 26, 2008
    Inventors: Ravi Kumar Arimilli, Robert Alan Cargnoni, Derek Edward Williams, Kenneth Lee Wright
  • Patent number: 7370155
    Abstract: A method and data processing system for sequentially coupling successive, homogenous processor requests for a cache line in a chain before the data is received in the cache of a first processor within the chain. Chained intermediate coherency states are assigned to track the chain of processor requests and subsequent access permission provided, prior to receipt of the data at the first processor starting the chain. The chained intermediate coherency state assigned identifies the processor operation and a directional identifier identifies the processor to which the cache line is to be forwarded. When the data is received at the cache of the first processor within the chain, the first processor completes its operation on (or with) the data and then forwards the data to the next processor in the chain. The chain is immediately stopped when a non-homogenous operation is snooped by the last-in-chain processor.
    Type: Grant
    Filed: October 6, 2005
    Date of Patent: May 6, 2008
    Assignee: International Business Machines Corporation
    Inventors: Ramakrishnan Rajamony, Hazim Shafi, Derek Edward Williams, Kenneth Lee Wright
  • Patent number: 7359932
    Abstract: A processor communication register (PCR) contained within a multiprocessor cluster system provides enhanced processor communication. The PCR stores information that is useful in pipelined or parallel multi-processing. Each processor cluster has exclusive rights to store to a sector within the PCR and has continuous access to read its contents. Each processor cluster updates its exclusive sector within the PCR, instantly allowing all of the other processors within the cluster network to see the change within the PCR data, and bypassing the cache subsystem. Efficiency is enhanced within the processor cluster network by providing processor communications to be immediately networked and transferred into all processors without momentarily restricting access to the information or forcing all the processors to be continually contending for the same cache line, and thereby overwhelming the interconnect and memory system with an endless stream of load, store and invalidate commands.
    Type: Grant
    Filed: December 12, 2002
    Date of Patent: April 15, 2008
    Assignee: International Business Machines Corporation
    Inventors: Ravi Kumar Arimilli, Robert Alan Cargnoni, Derek Edward Williams, Kenneth Lee Wright
  • Patent number: 7360067
    Abstract: A processor communication register (PCR) contained in each processor within a multiprocessor cluster network provides enhanced processor communication. Each PCR stores identical processor communication information that is useful in pipelined or parallel multi-processing. Each processor has exclusive rights to store to a sector within each PCR within the cluster network and has continuous access to read the contents of its own PCR. Each processor updates its exclusive sector within all of the PCRs via a private protocol or dedicated wireless network, instantly allowing all of the other processors within the cluster network to see the change within the PCR data, and bypassing the cache subsystem.
    Type: Grant
    Filed: December 12, 2002
    Date of Patent: April 15, 2008
    Assignee: International Business Machines Corporation
    Inventors: Ravi Kumar Arimilli, Robert Alan Cargnoni, Derek Edward Williams, Kenneth Lee Wright
  • Patent number: 7356568
    Abstract: A processor communication register (PCR) contained in each processor within a multiprocessor system provides enhanced processor communication. Each PCR stores identical processor communication information that is useful in pipelined or parallel multi-processing. Each processor has exclusive rights to store to a sector within each PCR and has continuous access to read the contents of its own PCR. Each processor updates its exclusive sector within all of the PCRs, instantly allowing all of the other processors to see the change within the PCR data, and bypassing the cache subsystem. Efficiency is enhanced within the multiprocessor system by providing processor communications to be immediately transferred into all processors without momentarily restricting access to the information or forcing all the processors to be continually contending for the same cache line, and thereby overwhelming the interconnect and memory system with an endless stream of load, store and invalidate commands.
    Type: Grant
    Filed: December 12, 2002
    Date of Patent: April 8, 2008
    Assignee: International Business Machines Corporation
    Inventors: Ravi Kumar Arimilli, Robert Alan Cargnoni, Derek Edward Williams, Kenneth Lee Wright
  • Patent number: 7284097
    Abstract: A cache coherency protocol that includes a modified-invalid (Mi) state, which enables execution of a DMA Claim or DClaim operation to assign sole ownership of a cache line to a device that is going to overwrite the entire cache line without cache-to-cache data transfer. The protocol enables completion of speculatively-issued full cache line writes without requiring cache-to-cache transfer of data on the data bus during a preceding DMA Claim or DClaim operation. The modified-invalid (Mi) state assigns sole ownership of the cache line to an I/O device that has speculatively-issued a DMA Write or a processor that has speculatively-issued a DCBZ operation to overwrite the entire cache line, and the Mi state prevents data being sent to the cache line from another cache since the data will most probably be overwritten.
    Type: Grant
    Filed: September 30, 2003
    Date of Patent: October 16, 2007
    Assignee: International Business Machines Corporation
    Inventors: John Steven Dodson, James Stephen Fields, Jr., Guy Lynn Guthrie, Kenneth Lee Wright
  • Patent number: 7243194
    Abstract: A method, system and computer program product for handling write requests in a data processing system is disclosed. The method comprises receiving on an interconnect bus a first write request targeted to a first address and receiving on the interconnect bus a subsequent second write request targeted to a subsequent second address. The subsequent second write request is completed prior to completing the first write request, and, responsive to receiving a read request targeting the second address before the first write request has completed, data associated with the second address of the second write request is supplied only after the first write request completes.
    Type: Grant
    Filed: February 9, 2005
    Date of Patent: July 10, 2007
    Assignee: International Business Machines Corporation
    Inventors: George William Daly, Jr., James Stephen Fields, Jr., Paul K. Umbarger, Kenneth Lee Wright
  • Patent number: 7194587
    Abstract: A microprocessor and a related compiler support a local cache block flush instruction in which an execution unit of a processor determines an effective address. The processor forces all pending references to a cache block corresponding to the determined effective address to commit to the cache subsystem. If the referenced cache line is modified in the local cache (the cache subsystem corresponding to the processor executing the instruction), it is then written back to main memory. If the referenced block is valid in the local cache it is invalidated, but only in the local cache. If the referenced block is not valid in the local cache, there is no invalidation. Remote processors receiving a local cache block flush instruction from another processor via the system ignore the instruction.
    Type: Grant
    Filed: April 24, 2003
    Date of Patent: March 20, 2007
    Assignee: International Business Machines Corp.
    Inventors: John David McCalpin, Balaram Sinharoy, Dereck Edward Williams, Kenneth Lee Wright