Abstract: An apparatus for influencing process scheduling in a data processing system capable of utilizing a virtual memory processing scheme is disclosed. The data processing system includes multiple processing units. The processing units have volatile cache memories operating in a virtual address space that is greater than a real address space. The processing units and the respective volatile memories are coupled to a storage controller operating in a physical address space that is equal to the virtual address space. The processing units and the storage controller are coupled to a hard disk via an interconnect. The storage controller, which is coupled to a physical memory cache, allows the mapping of a virtual address from one of the volatile cache memories to a physical disk address directed to a storage location within the hard disk without transitioning through a real address. The physical memory cache contains a subset of information within the hard disk.

Abstract: A processor communication register (PCR) contained within a multiprocessor cluster system provides enhanced processor communication. The PCR stores information that is useful in pipelined or parallel multi-processing. Each processor cluster has exclusive rights to store to a sector within the PCR and has continuous access to read its contents. Each processor cluster updates its exclusive sector within the PCR, instantly allowing all of the other processors within the cluster network to see the change within the PCR data, and bypassing the cache subsystem. Efficiency is enhanced within the processor cluster network by providing processor communications to be immediately networked and transferred into all processors without momentarily restricting access to the information or forcing all the processors to be continually contending for the same cache line, and thereby overwhelming the interconnect and memory system with an endless stream of load, store and invalidate commands.

Abstract: A processor communication register (PCR) contained in each processor within a multiprocessor system provides enhanced processor communication. Each PCR stores identical processor communication information that is useful in pipelined or parallel multi-processing. Each processor has exclusive rights to store to a sector within each PCR and has continuous access to read the contents of its own PCR. Each processor updates its exclusive sector within all of the PCRs, instantly allowing all of the other processors to see the change within the PCR data, and bypassing the cache subsystem. Efficiency is enhanced within the multiprocessor system by providing processor communications to be immediately transferred into all processors without momentarily restricting access to the information or forcing all the processors to be continually contending for the same cache line, and thereby overwhelming the interconnect and memory system with an endless stream of load, store and invalidate commands.

Abstract: A hardware managed virtual-to-physical address translation mechanism for a data processing system having no system memory is disclosed. The data processing system includes multiple processing units. The processing units have volatile cache memories operating in a virtual address space that is greater than a real address space. The processing units and the respective volatile memories are coupled to a storage controller operating in a physical address space. The processing units and the storage controller are coupled to a hard disk via an interconnect. The hard disk contains a virtual-to-physical translation table for translating a virtual address from one of said volatile cache memories to a physical disk address directed to a storage location in the hard disk without transitioning through a real address.

Abstract: A processor communication register (PCR) contained in each processor within a multiprocessor cluster network provides enhanced processor communication. Each PCR stores identical processor communication information that is useful in pipelined or parallel multi-processing. Each processor has exclusive rights to store to a sector within each PCR within the cluster network and has continuous access to read the contents of its own PCR. Each processor updates its exclusive sector within all of the PCRs via a private protocol or dedicated wireless network, instantly allowing all of the other processors within the cluster network to see the change within the PCR data, and bypassing the cache subsystem.

Abstract: An aliasing support for a data processing system having no system memory is disclosed. The data processing system includes multiple processing units. The processing units have volatile cache memories operating in a virtual address space that is greater than a real address space. The processing units and the respective volatile memories are coupled to a storage controller operating in a physical address space. The processing units and the storage controller are coupled to a hard disk via an interconnect. The processing units contains an aliasing table for associating at least two virtual addresses to a physical disk address directed to a storage location in the hard disk. The hard disk contains a virtual-to-physical translation table for translating a virtual address from one of said volatile cache memories to a physical disk address directed to a storage location in the hard disk without transitioning through a real address.

Abstract: A move engine and operating system transparently reconfigure physical memory to accomplish addition, subtraction, or replacement of a memory module. The operating system stores FROM and TO real addresses in unique fields in memory that are used to virtualize the physical address of the memory module being reconfigured and provide the reconfiguration in real-time through the use of hardware functionality and not software. Using the FROM and TO real addresses to select a source and a target, the move engine copies the contents of the memory module to be removed or reconfigured into the remaining or inserted memory module. Then, the real address associated with the reconfigured memory module is re-assigned to the memory module receiving the copied contents, thereby creating a virtualized physical mapping from the addressable real address space being utilized by the operating system into a virtual physical address space.

Abstract: A processor contains a move engine and a memory controller contains a mapping engine that, together, transparently reconfigure physical memory to accomplish addition, subtraction, or replacement of a memory module. A mapping engine register stores current and new real addresses that enable the engines to virtualize the physical address of the memory module being reconfigured and provide the reconfiguration in real-time through the use of hardware functionality and not software. Using the current and new real addresses to select a source and a target, the move engine copies the contents of the memory module to be removed or reconfigured into the remaining or inserted memory modules. Then, the real address associated with the reconfigured memory module is re-assigned to the memory module receiving the copied contents, thereby creating a virtualized physical mapping from the addressable real address space being utilized by the operating system into a virtual physical address space.

Abstract: A processor contains a move engine and mapping engine that transparently reconfigure physical memory to accomplish addition, subtraction, or replacement of a memory module. A mapping engine register stores FROM and TO real addresses that enable the engines to virtualize the physical address of the memory module being reconfigured and provide the reconfiguration in real-time through the use of hardware functionality and not software. Using the FROM and TO real addresses to select a source and a target, the move engine copies the contents of the memory module to be removed or reconfigured into the remaining or inserted memory module. Then, the real address associated with the reconfigured memory module is re-assigned to the memory module receiving the copied contents, thereby creating a virtualized physical mapping from the addressable real address space being utilized by the operating system into a virtual physical address space.

Abstract: In a method, system, and apparatus for managing storage of data elements, a storage area having a first and second end is provided for storing the data elements. In the storage area, a first stack of data elements has first and second ends respectively facing the first and second ends of the storage area, and a second stack has data elements located proximate both ends of the first stack. That is, the second stack is split, with the first stack interposed between data elements of the second stack. Likewise, there may be a third and fourth stack, and so on, which are split into more than one part. The stacks increase in size toward both the first end of the storage area and the second end of the storage area, responsive to the storing of successive ones of the data elements in the respective stacks. Furthermore, the increasing in size of one of the split stacks may include increasing away from the first stack, or alternatively, increasing toward the first stack.

Abstract: A method, system, and apparatus for managing data elements in a storage area is disclosed. A storage area, with a first and second end, is provided for storing data elements. The data elements are stored in a first stack, also having a first and second end. Space in the storage area for the first stack includes a first space proximate the first end of the first stack, and a second space proximate the second end of the first stack. The storing of one of the data elements in the first stack includes selecting between storing in the first space or the second space, responsive to the relative sizes of the two spaces. Data elements are also stored in the storage area in a second stack. Space available in the storage area for data elements of the second stack includes the above mentioned first and second spaces, that is, the space proximate the first end of the first stack, and the space proximate the second end of the first stack.

Abstract: A method and apparatus for dynamically driving events in a simulation of a data processing system are implemented. Events, or system states, are generated by drivers located at predetermined locations within the simulation model under test. These events, which are drawn from a predetermined class of events, termed “effects,” are driven in response to other events observed by monitors disposed within the simulation model in accordance with a predetermined set of “causes,” and a set of “rules” that map causes to effects. The driving of events is mediated by a library process that receives observed events from the monitors, in the form of data structures, stored them in a database, and passes the effects to be driven to the appropriate driver in accordance with the set of rules, also data structures stored in the database, when a cause corresponds to a observed event.

Abstract: A system and method for verifying cache coherency in a multi-node, NUMA system includes a transaction modification unit configured to receive event traces generated by a simulation tool. The modification unit modifies transactions that are propagated to another node in the NUMA system and thus result in two bus transactions, a home node transaction (HNT) and a foreign node transaction (FNT). More specifically, the modification unit merges a FNT and its corresponding HNT into a single merge transaction (MT) under a prescribed set of merging rules. The MT has properties of the both the FNT and the HNT. The FNT and HNT are deleted from the event trace and replaced by their corresponding MT to create a modified event trace that is suitable for coherency checking by a single system coherency checker.

Abstract: A method, computer program product and data processing system for verifying cumulative ordering. In one embodiment of the present invention a method comprises the step of selecting a memory barrier instruction issued by a particular processor. The method further comprises selecting a first cache line out of a plurality of cache lines to be paired with one or more of the remaining of the plurality of cache lines. If a load memory instruction executed after the memory barrier instruction in the first cache line was identified, then the first cache line selected will be paired with a second cache line. If a load memory instruction executed before the memory barrier instruction in the second cache line was identified, then a pair of load memory instructions has been identified. Upon identifying the second load memory instruction, a first and second reload of the first and second cache lines are identified.