Patents by Inventor Kenneth M. Valk
Kenneth M. Valk has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 11341060Abstract: In a data processing environment, a communication interface of a second host data processing system receives, from a first host data processing system, a host command in a first command set. The host command specifies a memory access to a memory coupled to the second host data processing system. The communication interface translates the host command into a command in a different second command set emulating coupling of an attached functional unit to the communication interface. The communication interface presents the second command to a host bus protocol interface of the second host data processing system. Based on receipt of the second command, the host bus protocol interface initiates, on a system fabric of the second host data processing system, a host bus protocol memory access request specifying the memory access.Type: GrantFiled: August 11, 2020Date of Patent: May 24, 2022Assignee: International Business Machines CorporationInventors: Michael S. Siegel, William J. Starke, Jeffrey A. Stuecheli, Lakshminarayana Arimilli, Kenneth M. Valk, James Mikos, David Krolak
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Publication number: 20220050787Abstract: In a data processing environment, a communication interface of a second host data processing system receives, from a first host data processing system, a host command in a first command set. The host command specifies a memory access to a memory coupled to the second host data processing system. The communication interface translates the host command into a command in a different second command set emulating coupling of an attached functional unit to the communication interface. The communication interface presents the second command to a host bus protocol interface of the second host data processing system. Based on receipt of the second command, the host bus protocol interface initiates, on a system fabric of the second host data processing system, a host bus protocol memory access request specifying the memory access.Type: ApplicationFiled: August 11, 2020Publication date: February 17, 2022Inventors: Michael S. Siegel, William J. Starke, Jeffrey A. Stuecheli, Lakshminarayana Arimilli, Kenneth M. Valk, James Mikos, David Krolak
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Patent number: 11113204Abstract: An integrated circuit includes a first communication interface for communicatively coupling the integrated circuit with a coherent data processing system, a second communication interface for communicatively coupling the integrated circuit with an accelerator unit including an accelerator functional unit and an effective address-based accelerator cache for buffering copies of data from the system memory of the coherent data processing system, and a real address-based directory inclusive of contents of the accelerator cache. The real address-based directory assigns entries based on real addresses utilized to identify storage locations in the system memory.Type: GrantFiled: April 18, 2019Date of Patent: September 7, 2021Assignee: International Business Machines CorporationInventors: Bartholomew Blaner, Michael S. Siegel, Jeffrey A. Stuecheli, William J. Starke, Kenneth M. Valk, John D. Irish, Lakshminarayana Arimilli
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Patent number: 11095571Abstract: IEEE 802.1Q and Enhanced Transmission Selection provide only eight different traffic classes that may be used to control bandwidth in a particular physical connection (or link). Instead of relying only on these eight traffic classes to manage bandwidth, the embodiments discussed herein disclose using an Enhanced Transmission Selection scheduler that permits a network device to set the bandwidth for an individual virtual LAN. Allocating bandwidth in a port based on a virtual LAN ID permits a network device to allocate bandwidth to, e.g., millions of unique virtual LANs. Thus, this technique may increase the granular control of the network fabric and its performance.Type: GrantFiled: November 2, 2017Date of Patent: August 17, 2021Assignee: International Business Machines CorporationInventors: William J. Armstrong, Claude Basso, Chih-Jen Chang, Mircea Gusat, Cyriel J. Minkenberg, Fredy D. Neeser, Kenneth M. Valk
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Patent number: 11030110Abstract: An integrated circuit includes a first communication interface for communicatively coupling the integrated circuit with a coherent data processing system, a second communication interface for communicatively coupling the integrated circuit with an accelerator unit including an effective address-based accelerator cache for buffering copies of data from a system memory, and a real address-based directory inclusive of contents of the accelerator cache. The real address-based directory assigns entries based on real addresses utilized to identify storage locations in the system memory. The integrated circuit further includes request logic that communicates memory access requests and request responses with the accelerator unit.Type: GrantFiled: April 26, 2019Date of Patent: June 8, 2021Assignee: International Business Machines CorporationInventors: Michael S. Siegel, Bartholomew Blaner, Jeffrey A. Stuecheli, William J. Starke, Derek E. Williams, Kenneth M. Valk, John D. Irish, Lakshminarayana Arimilli
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Patent number: 10846235Abstract: An integrated circuit for a coherent data processing system includes a first communication interface for communicatively coupling the integrated circuit with the coherent data processing system, a second communication interface for communicatively coupling the integrated circuit with an accelerator unit including an effective address-based accelerator cache for buffering copies of data from a system memory of the coherent data processing system, and a real address-based directory inclusive of contents of the accelerator cache. The real address-based directory assigns entries based on real addresses utilized to identify storage locations in the system memory. The integrated circuit further includes request logic that communicates memory access requests and request responses with the accelerator unit via the second communication interface.Type: GrantFiled: March 15, 2019Date of Patent: November 24, 2020Assignee: International Business Machines CorporationInventors: Bartholomew Blaner, Michael S. Siegel, Jeffrey A. Stuecheli, William J. Starke, Kenneth M. Valk, John D. Irish, Lakshminarayana Arimilli
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Patent number: 10834008Abstract: In one embodiment, a method includes receiving a plurality of flows, each flow comprising packets of data and assigning a service credit to each of the plurality of flows. In addition, the method includes assigning a weight parameter to each of the plurality of flows, and selecting a flow from a head of a first control queue unless the first control queue is empty or there is indication that the first control queue should be avoided. A flow is selected from a head of a second control queue in response to a determination that the first control queue is empty or there is indication that the first control queue should be avoided. Additionally, the method includes providing a number of units of service to the selected flow. Moreover, the method includes decreasing the selected flow's service credit by an amount corresponding to the number of units of service provided thereto.Type: GrantFiled: November 8, 2017Date of Patent: November 10, 2020Assignee: International Business Machines CorporationInventors: Claude Basso, Nikolaos Chrysos, Casimer M. DeCusatis, Mircea Gusat, Keshav G. Kamble, Cyriel J. Minkenberg, Fredy D. Neeser, Kenneth M. Valk
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Patent number: 10761995Abstract: An integrated circuit includes a first communication interface for communicatively coupling the integrated circuit with a coherent data processing system, a second communication interface for communicatively coupling the integrated circuit with an accelerator unit including an effective address-based accelerator cache for buffering copies of data from a system memory, and a real address-based directory inclusive of contents of the accelerator cache. The real address-based directory assigns entries based on real addresses utilized to identify storage locations in the system memory. The integrated circuit further includes directory control logic that configures at least a number of congruence classes utilized in the real address-based directory based on configuration parameters specified on behalf of or by the accelerator unit.Type: GrantFiled: April 26, 2019Date of Patent: September 1, 2020Assignee: International Business Machines CorporationInventors: Bartholomew Blaner, Jeffrey A. Stuecheli, Michael S. Siegel, William J. Starke, Curtis C. Wollbrink, Kenneth M. Valk, Lakshminarayana Arimilli, John D. Irish
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Patent number: 10613979Abstract: A claw-back request, received from an accelerator, is issued for an address line. While waiting for a response to the claw-back request, a cast-out push request with a matching address line is received. The cast-out push request is associated with a cache having a modified copy of the address line. A combined-response, associated with the cast-out push request, is received from a bus. Data associated with the modified copy of the address line is received from the cache. A claw-back response, with the data associated with the modified version of the address line, is issued to an accelerator.Type: GrantFiled: November 30, 2017Date of Patent: April 7, 2020Assignee: International Business Machines CorporationInventors: Kenneth M. Valk, Guy L. Guthrie, Derek E. Williams, Michael S. Siegel, John D. Irish
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Publication number: 20190332549Abstract: An integrated circuit includes a first communication interface for communicatively coupling the integrated circuit with a coherent data processing system, a second communication interface for communicatively coupling the integrated circuit with an accelerator unit including an effective address-based accelerator cache for buffering copies of data from a system memory, and a real address-based directory inclusive of contents of the accelerator cache. The real address-based directory assigns entries based on real addresses utilized to identify storage locations in the system memory. The integrated circuit further includes directory control logic that configures at least a number of congruence classes utilized in the real address-based directory based on configuration parameters specified on behalf of or by the accelerator unit.Type: ApplicationFiled: April 26, 2019Publication date: October 31, 2019Inventors: BARTHOLOMEW BLANER, JEFFREY A. STUECHELI, MICHAEL S. SIEGEL, WILLIAM J. STARKE, CURTIS C. WOLLBRINK, KENNETH M. VALK, LAKSHMINARAYANA ARIMILLI, JOHN D. IRISH
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Publication number: 20190332537Abstract: An integrated circuit for a coherent data processing system includes a first communication interface for communicatively coupling the integrated circuit with the coherent data processing system, a second communication interface for communicatively coupling the integrated circuit with an accelerator unit including an effective address-based accelerator cache for buffering copies of data from a system memory of the coherent data processing system, and a real address-based directory inclusive of contents of the accelerator cache. The real address-based directory assigns entries based on real addresses utilized to identify storage locations in the system memory. The integrated circuit further includes request logic that communicates memory access requests and request responses with the accelerator unit via the second communication interface.Type: ApplicationFiled: March 15, 2019Publication date: October 31, 2019Inventors: BARTHOLOMEW BLANER, MICHAEL S. SIEGEL, JEFFREY A. STUECHELI, WILLIAM J. STARKE, KENNETH M. VALK, JOHN D. IRISH, LAKSHMINARAYANA ARIMILLI
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Publication number: 20190332551Abstract: An integrated circuit includes a first communication interface for communicatively coupling the integrated circuit with a coherent data processing system, a second communication interface for communicatively coupling the integrated circuit with an accelerator unit including an effective address-based accelerator cache for buffering copies of data from a system memory, and a real address-based directory inclusive of contents of the accelerator cache. The real address-based directory assigns entries based on real addresses utilized to identify storage locations in the system memory. The integrated circuit further includes request logic that communicates memory access requests and request responses with the accelerator unit.Type: ApplicationFiled: April 26, 2019Publication date: October 31, 2019Inventors: MICHAEL S. SIEGEL, BARTHOLOMEW BLANER, JEFFREY A. STUECHELI, WILLIAM J. STARKE, DEREK E. WILLIAMS, KENNETH M. VALK, JOHN D. IRISH, LAKSHMINARAYANA ARIMILLI
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Publication number: 20190332548Abstract: An integrated circuit includes a first communication interface for communicatively coupling the integrated circuit with a coherent data processing system, a second communication interface for communicatively coupling the integrated circuit with an accelerator unit including an accelerator functional unit and an effective address-based accelerator cache for buffering copies of data from the system memory of the coherent data processing system, and a real address-based directory inclusive of contents of the accelerator cache. The real address-based directory assigns entries based on real addresses utilized to identify storage locations in the system memory.Type: ApplicationFiled: April 18, 2019Publication date: October 31, 2019Inventors: BARTHOLOMEW BLANER, MICHAEL S. SIEGEL, JEFFREY A. STUECHELI, WILLIAM J. STARKE, KENNETH M. VALK, JOHN D. IRISH, LAKSHMINARAYANA ARIMILLI
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Publication number: 20190163633Abstract: A claw-back request, received from an accelerator, is issued for an address line. While waiting for a response to the claw-back request, a cast-out push request with a matching address line is received. The cast-out push request is associated with a cache having a modified copy of the address line. A combined-response, associated with the cast-out push request, is received from a bus. Data associated with the modified copy of the address line is received from the cache. A claw-back response, with the data associated with the modified version of the address line, is issued to an accelerator.Type: ApplicationFiled: November 30, 2017Publication date: May 30, 2019Inventors: Kenneth M. Valk, Guy L. Guthrie, Derek E. Williams, Michael S. Siegel, John D. Irish
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Patent number: 10216653Abstract: A serial communication system includes a transmitting circuit for serially transmitting data via a serial communication link including N channels where N is an integer greater than 1. The transmitting circuit includes an input buffer having storage for input data frames each including M bytes forming N segments of M/N contiguous bytes. The transmitting circuit additionally includes a reordering circuit coupled to the input buffer. The reordering circuit includes a reorder buffer including multiple entries. The reordering circuit buffers, in each of multiple entries of the reorder buffer, a byte in a common byte position in each of the N segments of an input data frame. The reordering circuit sequentially outputs the contents of the entries of the reorder buffer via the N channels of the serial communication link.Type: GrantFiled: October 3, 2017Date of Patent: February 26, 2019Assignee: International Busiess Machines CorporationInventors: Lakshminarayana Baba Arimilli, Yiftach Benjamini, Bartholomew Blaner, Daniel M. Dreps, John David Irish, David J. Krolak, Lonny Lambrecht, Michael S. Siegel, William J. Starke, Jeffrey A. Stuecheli, Kenneth M. Valk, Curtis C. Wollbrink
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Publication number: 20180145926Abstract: IEEE 802.1Q and Enhanced Transmission Selection provide only eight different traffic classes that may be used to control bandwidth in a particular physical connection (or link). Instead of relying only on these eight traffic classes to manage bandwidth, the embodiments discussed herein disclose using an Enhanced Transmission Selection scheduler that permits a network device to set the bandwidth for an individual virtual LAN. Allocating bandwidth in a port based on a virtual LAN ID permits a network device to allocate bandwidth to, e.g., millions of unique virtual LANs. Thus, this technique may increase the granular control of the network fabric and its performance.Type: ApplicationFiled: November 2, 2017Publication date: May 24, 2018Inventors: William J. ARMSTRONG, Claude BASSO, Chih-Jen CHANG, Mircea GUSAT, Cyriel J. MINKENBERG, Fredy D. NEESER, Kenneth M. VALK
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Publication number: 20180095905Abstract: A serial communication system includes a transmitting circuit for serially transmitting data via a serial communication link including N channels where N is an integer greater than 1. The transmitting circuit includes an input buffer having storage for input data frames each including M bytes forming N segments of M/N contiguous bytes. The transmitting circuit additionally includes a reordering circuit coupled to the input buffer. The reordering circuit includes a reorder buffer including multiple entries. The reordering circuit buffers, in each of multiple entries of the reorder buffer, a byte in a common byte position in each of the N segments of an input data frame. The reordering circuit sequentially outputs the contents of the entries of the reorder buffer via the N channels of the serial communication link.Type: ApplicationFiled: October 3, 2017Publication date: April 5, 2018Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: LAKSHMINARAYANA BABA ARIMILLI, YIFTACH BENJAMINI, BARTHOLOMEW BLANER, DANIEL M. DREPS, JOHN DAVID IRISH, DAVID J. KROLAK, LONNY LAMBRECHT, MICHAEL S. SIEGEL, WILLIAM J. STARKE, JEFFREY A. STUECHELI, KENNETH M. VALK, CURTIS C. WOLLBRINK
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Publication number: 20180069802Abstract: In one embodiment, a method includes receiving a plurality of flows, each flow comprising packets of data and assigning a service credit to each of the plurality of flows. In addition, the method includes assigning a weight parameter to each of the plurality of flows, and selecting a flow from a head of a first control queue unless the first control queue is empty or there is indication that the first control queue should be avoided. A flow is selected from a head of a second control queue in response to a determination that the first control queue is empty or there is indication that the first control queue should be avoided. Additionally, the method includes providing a number of units of service to the selected flow. Moreover, the method includes decreasing the selected flow's service credit by an amount corresponding to the number of units of service provided thereto.Type: ApplicationFiled: November 8, 2017Publication date: March 8, 2018Inventors: Claude Basso, Nikolaos Chrysos, Casimer M. DeCusatis, Mircea Gusat, Keshav G. Kamble, Cyriel J. Minkenberg, Fredy D. Neeser, Kenneth M. Valk
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Patent number: 9860188Abstract: IEEE 802.1Q and Enhanced Transmission Selection provide only eight different traffic classes that may be used to control bandwidth in a particular physical connection (or link). Instead of relying only on these eight traffic classes to manage bandwidth, the embodiments discussed herein disclose using an Enhanced Transmission Selection scheduler that permits a network device to set the bandwidth for an individual virtual LAN. Allocating bandwidth in a port based on a virtual LAN ID permits a network device to allocate bandwidth to, e.g., millions of unique virtual LANs. Thus, this technique may increase the granular control of the network fabric and its performance.Type: GrantFiled: December 22, 2011Date of Patent: January 2, 2018Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: William J. Armstrong, Claude Basso, Chih-Jen Chang, Mircea Gusat, Cyriel J. Minkenberg, Fredy D. Neeser, Kenneth M. Valk
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Patent number: 9843529Abstract: In one embodiment, a method includes selecting a flow from a head of a first control queue or a second control queue. The method also includes providing service to the selected flow. Moreover, the method includes decreasing a service credit of the selected flow by an amount corresponding to an amount of service provided to the selected flow. In another embodiment, a computer program product includes a computer readable storage medium having program code embodied therewith. The embodied program code is readable/executable by a device to select, by the device, a flow from a head of a first control queue or a second control queue. The embodied program code is also readable/executable to provide, by the device, service to the selected flow, and decrease, by the device, a service credit of the selected flow by an amount corresponding to an amount of service provided to the selected flow.Type: GrantFiled: October 6, 2015Date of Patent: December 12, 2017Assignee: International Business Machines CorporationInventors: Claude Basso, Nikolaos Chrysos, Casimer M. DeCusatis, Mircea Gusat, Keshav G. Kamble, Cyriel J. Minkenberg, Fredy D. Neeser, Kenneth M. Valk