Abstract: A method is provided for processing a command issued by a processor over a bus. The method includes (1) transmitting the command to a remote node to obtain access to data required to complete the command; (2) receiving from the remote node a response packet including a header and a variable gap; and (3) before receiving the data required to complete the command, arranging to return the data to the processor over the bus.

Abstract: A technique for handling commands includes assigning respective first tags to ordered commands included in an ordered command stream. Respective second tags are then assigned to subsequent commands that follow an initial command (included in the ordered commands). Each of the respective second tags correspond to one the respective first tags that is associated with an immediate previous one of the ordered commands. The initial command is sent to an execution engine in a first cycle. At least one of the subsequent commands is sent to the execution engine prior to completion of execution of the initial command.

Abstract: A memory controller receives a stream of DMA write operations and enqueues them in a queue enforcing a First-In First-Out (FIFO) order. Prior to processing a particular DMA write operation, the memory controller acquires coherency ownership of a target memory block and stores the result in a low latency array. In response to acquiring coherency ownership, this low latency array is updated to a coherency state signifying coherency ownership by the memory controller. In a pipelined array access, both the low latency array and the second array are accessed and if the lower latency second array indicates the particular coherency state with no collision indication, the memory controller signals that the particular DMA write operation can be performed, where the signaling occurs prior to results being obtained from the higher latency first array at the normal end of the array access pipeline.

Abstract: A multiprocessor data processing system includes a memory controller controlling access to a memory subsystem, multiple processor buses coupled to the memory controller, and at least one of multiple processors coupled to each processor bus. In response to receiving a first read request of a first processor via a first processor bus, the memory controller initiates a speculative access to the memory subsystem and a lookup of the target address in a central coherence directory. In response to the central coherence directory indicating that a copy of the target memory block is cached by a second processor, the memory controller transmits a second read request for the target address on a second processor bus. In response to receiving a clean snoop response to the second read request, the memory controller provides to the first processor the target memory block retrieved from the memory subsystem by the speculative access.

Abstract: A method and apparatus are provided for maintaining a N-way associative directory utilizing a content addressable memory (CAM). A congruence class from the N-way associative directory including a directory entry identified for a data operation is read into the CAM for the data operation. The directory entry for the data operation in the CAM is locked while the data operation is pending. Other entries in the congruence class are available. When the data operation is completed, checking for a state change is performed. Responsive to an identified state change, the directory entry for the data operation in the CAM is updated or marked as changed. The congruence class including the updated directory entry is marked as dirty. In accordance with features of the invention, the changed congruence class directory entries in the CAM are accumulated and scheduled to be written back to the N-way associative directory.