Patents by Inventor Kenneth P Parker

Kenneth P Parker has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 7518384
    Abstract: One or more test probe access structures for accessing vias on a printed circuit assembly and method of fabrication thereof is presented. Each test probe access structure is conductively connected to a via at a test probe access location above an exposed surface of a via to be accessible for probing by a test probe.
    Type: Grant
    Filed: January 31, 2005
    Date of Patent: April 14, 2009
    Assignee: Agilent Technologies, Inc.
    Inventors: Glen E Leinbach, Kenneth P Parker
  • Patent number: 7504589
    Abstract: A test access point structure for accessing test points of a printed circuit board and method of fabrication thereof is presented. Each test access point structure is conductively connected to a trace at a test access point and above an exposed surface of the printed circuit board to be accessible for probing by a fixture probe. The test access point structure may be designed and manufactured to permit deformation of the test access point structure upon initial probing of the test access point structure with a fixture probe to ensure electrical contact between the fixture probe and the test access point structure.
    Type: Grant
    Filed: October 25, 2004
    Date of Patent: March 17, 2009
    Assignee: Agilent Technologies, Inc.
    Inventors: Kenneth P. Parker, Chris R. Jacobsen
  • Publication number: 20080315892
    Abstract: A method of testing for shorts between nodes of a circuit assembly includes parsing circuit design data to identify positional data for nodes of a circuit assembly, and using the positional data to classify ones of the nodes as members of a supernode, where each member of the supernode is unlikely to be shorted to any other member of the supernode. Tests for shorts in a set of nodes that includes the supernode and a plurality of other nodes of the circuit assembly are then conducted, by iteratively i) stimulating a particular one of the set of nodes, and ii) while stimulating the particular node, grounding at least one other node in the set of nodes and monitoring a current flow through the particular node. When stimulating or grounding a supernode, all of the nodes that are members of the supernode are stimulated or grounded. If a current flow is detected through one of the stimulated nodes, the circuit assembly is indicated to be defective. Other embodiments are also disclosed.
    Type: Application
    Filed: January 30, 2008
    Publication date: December 25, 2008
    Inventors: Kenneth P. Parker, Chris Richard Jacobsen
  • Publication number: 20080297168
    Abstract: In one embodiment, a method for testing a differential signaling channel having a differential pair of signal paths, and a pair of signal grounds bounding the differential pair, includes: causing positive and negative phases of a differential waveform to be driven over respective paths of the differential pair while monitoring a signal induced in a capacitive sense plate positioned adjacent to, and capacitively coupled to, all of the paths and grounds of the channel; when an amplitude of the monitored signal is within a first range, indicating to a user that there are no open defects in the differential signaling channel; and when the amplitude of the monitored signal falls within one or more second ranges, and not within the first range, indicating to the user that an open exists in the differential signaling channel. Other embodiments are also disclosed.
    Type: Application
    Filed: January 30, 2008
    Publication date: December 4, 2008
    Inventor: Kenneth P. Parker
  • Patent number: 7437638
    Abstract: Disclosed herein are various methods and apparatus related to Boundary-Scan testing, including a method for generating Boundary-Scan test vectors. The method assigns different binary signatures to all of the drivers and hysteretic test receiver memories of a circuit assembly under test, and then generates a series of Boundary-Scan test vectors wherein each test vector is derived from corresponding bits of the binary signatures.
    Type: Grant
    Filed: November 12, 2002
    Date of Patent: October 14, 2008
    Assignee: Agilent Technologies, Inc.
    Inventor: Kenneth P. Parker
  • Publication number: 20080148208
    Abstract: Techniques for automating test pad insertion in a printed circuit board (PCB) design and fixture probes insertion in a PCB tester fixture are presented. A probe location algorithm predictably determines respective preferred probing locations from among respective sets of potential probing locations associated with a number of respective nets in a PCB design. Test pads, preferably in the form of bead probes, are added to the PCB design at the respective preferred probing locations along with, where feasible, one or more alternate probing locations chosen from among remaining ones of the respective sets of potential probing locations. During fixture design, nets with multiple test pads implemented in the PCB design are processed by the same probe location algorithm used during PCB design to determine the associated preferred probing location and any associated alternate probing locations for said respective nets.
    Type: Application
    Filed: January 22, 2008
    Publication date: June 19, 2008
    Inventors: Chris R. Jacobsen, Kenneth P. Parker, John E. Herczeg
  • Patent number: 7362106
    Abstract: A method and apparatus for detecting open defects on non-probed node under test of an electrical device using capacitive lead frame technology is presented. In accordance with the method of the invention, a probed node neighboring the non-probed node under test is stimulated with a known source signal. A sensor of a capacitive sensing probe is capacitively coupled to at least the probed node and non-probed node under test of the electrical device, and a measuring device coupled to the capacitive sensing probe measures a capacitively coupled signal present between the sensor of the probe and at least the probed and non-probed node of the electrical device. Based on the value of the capacitively sensed signal, a known expected “defect-free” capacitively sensed signal measurement and/or a known expected “open” capacitively sensed signal measurement, a determination is made of whether an open defect exists on the non-probed node under test of the electrical device.
    Type: Grant
    Filed: June 29, 2005
    Date of Patent: April 22, 2008
    Assignee: Agilent Technologies, Inc.
    Inventors: Kenneth P. Parker, Myron J. Schneider
  • Patent number: 7325219
    Abstract: Techniques for automating probing location selection during printed circuit board (PCB) and corresponding PCB tester fixture design are presented. The invention includes a system and algorithm for selecting a probe layout comprising a set of probing locations for a printed circuit board design having a plurality of nets, at least some of which have a number of alternative possible probing locations. The system and algorithm iteratively generates a potential probe layout comprising one or more probing locations per net, and based on the potential probe layout, determines one or more regions of maximum deflection. A probing location from the potential probe layout that is located in a region of maximum deflection and is associated with a net having one or more alternative probing locations is removed from the potential probe layout and replaced in the with one of the one or more alternate probing locations associated with the net.
    Type: Grant
    Filed: February 16, 2005
    Date of Patent: January 29, 2008
    Assignee: Agilent Technologies, Inc.
    Inventors: Chris R. Jacobsen, Kenneth P. Parker
  • Patent number: 7307222
    Abstract: A test access point structure for accessing test points of a printed circuit board and method of fabrication thereof is presented. In an x-, y-, z-coordinate system where traces are printed along an x-y plane, the z-dimension is used to implement test access point structures. Each test access point structure is conductively connected to a trace at a test access point directly on top of the trace and along the z axis of the x-, y-, z-coordinate system above an exposed surface of the printed circuit board to be accessible for electrical probing by an external device.
    Type: Grant
    Filed: September 24, 2003
    Date of Patent: December 11, 2007
    Assignee: Agilent Technologies, Inc.
    Inventors: Kenneth P. Parker, Ronald J. Peiffer, Glen E. Leinbach
  • Patent number: 7307426
    Abstract: A method and apparatus for detecting open defects on grounded nodes of an electrical device using capacitive lead frame technology is presented. In accordance with the method of the invention, an accessible signal node that is capacitively coupled the grounded node is stimulated with a known source signal. A capacitive sense plate is capacitively coupled to the stimulated node and grounded node of the electrical device, and a measuring device coupled to the capacitive sense plate capacitively senses a resulting signal. The value of the capacitively sensed signal is indicative of the presence or non-presence of an open defect on one or both of the grounded node and stimulated signal node.
    Type: Grant
    Filed: July 12, 2005
    Date of Patent: December 11, 2007
    Assignee: Agilent Technologies, Inc.
    Inventors: Kenneth P. Parker, Chris R. Jacobsen
  • Patent number: 7307427
    Abstract: A method and apparatus is presented for gaining socket testability through the use of a capacitive interposer engineered to create capacitive coupling between signal nodes of a circuit assembly that the tester has access to and nodes of the socket that would not otherwise have any coupling to a testable signal node of the socket. Generally, coupling capacitance is engineered into the interposer by trace and via routing between the signal node of the socket and a location in close proximity to the inaccessible socket node such that their proximity to each other couples them together.
    Type: Grant
    Filed: July 23, 2005
    Date of Patent: December 11, 2007
    Assignee: Agilent Technologies, Inc.
    Inventors: Chris R. Jacobsen, Kenneth P. Parker, Myron J. Schneider, Tak Yee Kwan
  • Patent number: 7295031
    Abstract: Non-contact connectivity testing of joints connecting circuit junctions are improved through knowledge of characteristics of semiconductor junctions connected to component nodes of components of a device under test (DUT) to allow detection of high-impedance joints.
    Type: Grant
    Filed: July 12, 2006
    Date of Patent: November 13, 2007
    Assignee: Agilent Technologies, Inc.
    Inventors: Kenneth P. Parker, Chris R. Jacobsen, Dayton Norrgard, Myron J. Schneider
  • Patent number: 7259576
    Abstract: A twisting fixture probe for cleaning oxides, residues or other contaminants from the surface of a solder bead probe and probing a solder bead probe on a printed circuit board during in-circuit testing.
    Type: Grant
    Filed: March 14, 2005
    Date of Patent: August 21, 2007
    Assignee: Agilent Technologies, Inc.
    Inventors: Kenneth P Parker, Chris R Jacobsen
  • Patent number: 7224169
    Abstract: A method and apparatus for detecting shorts between accessible and inaccessible signal nodes (e.g., integrated circuit pins) of an electrical device (e.g., an integrated circuit), using capacitive lead frame technology is presented. In accordance with the method of the invention, an accessible node under test is stimulated with a known source signal. A capacitive sense plate is capacitively coupled to at least one of the accessible node and inaccessible node of the electrical device, and a measuring device coupled to the capacitive sense plate capacitively senses a signal present on the at least one of the accessible node and inaccessible node of the electrical device. Based on the value of the capacitively sensed signal, a known expected “defect-free” capacitively sensed signal measurement and/or a known expected “shorted” capacitively sensed signal measurement, one can determine whether a short fault exists between the accessible node and inaccessible node of the electrical device.
    Type: Grant
    Filed: November 2, 2004
    Date of Patent: May 29, 2007
    Assignee: Agilent Technologies, Inc.
    Inventor: Kenneth P. Parker
  • Patent number: 7208957
    Abstract: A method for testing for a defect condition on a node-under-implicit-test of an electrical device is presented. The technique according to the invention includes stimulating a first node of the electrical device that is capacitively coupled to the node-under-implicit-test with a known source signal, and capacitively sensing a signal on a second node of the electrical device that is capacitively coupled to the node-under-implicit-test. A defect condition such as a short or open can be determined from the capacitively sensed signal.
    Type: Grant
    Filed: March 1, 2005
    Date of Patent: April 24, 2007
    Assignee: Agilent Technologies, Inc.
    Inventors: Myron J. Schneider, Kenneth P. Parker, Chris R. Jacobsen
  • Patent number: 7190157
    Abstract: A layout independent test access point structure for accessing test points of a printed circuit board and method of fabrication thereof is presented. Each test access point structure is conductively connected to various locations along a trace at a test access point and above an exposed surface of the printed circuit board to be accessible for probing by a fixture probe.
    Type: Grant
    Filed: October 25, 2004
    Date of Patent: March 13, 2007
    Assignee: Agilent Technologies, Inc.
    Inventor: Kenneth P. Parker
  • Patent number: 7187165
    Abstract: Techniques for automating test pad insertion in a printed circuit board (PCB) design and fixture probe insertion in a PCB tester fixture are presented. A probe location algorithm predictably determines respective preferred probing locations from among respective sets of potential probing locations associated with a number of respective nets in a PCB design. Test pads, preferably in the form of bead probes, are added to the PCB design at the respective preferred probing locations along with, where feasible, one or more alternate probing locations chosen from among remaining ones of the respective sets of potential probing locations. During fixture design, nets with multiple test pads implemented in the PCB design are processed by the same probe location algorithm used during PCB design to determine the associated preferred and alternate probing locations for said respective nets.
    Type: Grant
    Filed: December 10, 2004
    Date of Patent: March 6, 2007
    Assignee: Agilent Technologies, Inc.
    Inventors: Chris R. Jacobsen, Kenneth P. Parker, John E. Herczeg
  • Patent number: 7170298
    Abstract: In one embodiment, a method for testing continuity of electrical paths through a circuit assembly includes: 1) mating a test-facilitating circuit package to a connector of the circuit assembly; the circuit package having a plurality of contacts for mating to a plurality of contacts of the connector; the circuit package containing incomplete or no mission circuitry for the circuit assembly, but containing a plurality of passive circuit components coupled in parallel between the package's plurality of contacts and a test sensor port of the circuit package; 2) stimulating one or more nodes of the circuit assembly; 3) measuring an electrical characteristic of the circuit package; and 4) comparing the measured electrical characteristic to at least one threshold to assess continuities of at least two electrical paths through the circuit assembly. Other embodiments are also disclosed.
    Type: Grant
    Filed: July 5, 2005
    Date of Patent: January 30, 2007
    Assignee: Agilent Technologies, Inc.
    Inventors: Kenneth P. Parker, Jacob L. Bell
  • Patent number: 7161369
    Abstract: A method and apparatus for a wiping fixture probe for cleaning oxides, residues or other contaminants from the surface of a solder bead probe and probing a solder bead probe on a printed circuit board during in-circuit testing.
    Type: Grant
    Filed: October 29, 2004
    Date of Patent: January 9, 2007
    Assignee: Agilent Technologies, Inc.
    Inventors: Kenneth P. Parker, Richard W. Rivas, Sr.
  • Patent number: 7137052
    Abstract: Structural testing can lead to high and abnormal current surges. Disclosed herein are methods for designing and testing an IC so that current surges therein may be minimized while the IC is being tested. One disclosed way to minimize current surges is by gating out shift induced node state transitions. Another disclosed way to minimize current surges is to operate two or more of an IC's scan chains in parallel, but out-of-phase.
    Type: Grant
    Filed: July 19, 2001
    Date of Patent: November 14, 2006
    Assignee: Verigy IPco
    Inventor: Kenneth P. Parker