Abstract: An electromagnetic probe is integrated within an integrated circuit or mounted within an IC package to provide a capability for testing continuity between the integrated circuit and a substrate to which the integrated circuit is mounted. In a first embodiment, capacitive test probes are integrated within the integrated circuit, underneath bonding pads. In a second embodiment, Hall-effect devices are integrated within the integrated circuit underneath bonding pads. In a third embodiment, an inductive loop is integrated within the integrated circuit underneath bonding pads. In a fourth embodiment, an IC package assembly includes an internal capacitive test probe for electrical continuity testing. An internal shield may also be used as a capacitive test probe. In a fifth embodiment, an IC package assembly includes an inductive loop within the package for electrical continuity testing.

Abstract: A method of testing series passive components in electronic assemblies. Only one test pin per passive component is required, thereby reducing the cost and complexity of test fixtures and the electronic assemblies. A passive component is connected between the output of a driving circuit and (optionally) an input of a receiving circuit. The output of the driving circuit is placed in a low impedance state. The receiving end of the passive component is stimulated and the response is measured. For reactive components, the stimulus and response are AC. For resistors, multiple DC measurements may be made. A optional DC bias may be provided to limit DC current and to further reduce the small signal output impedance of the driving circuit.

Abstract: A boundary scan testing device is presented which does not provide a boundary scan test vector generating function for producing boundary scan test vectors corresponding to the boundary scan device under test. Instead, the boundary scan testing device operates based on test vectors produced elsewhere.

Abstract: A method for generating improved detection and diagnostic test patterns and for improving the diagnostic resolution of interconnect testing of a circuit is based on the premise that short-circuits are most likely to result from solder bridges between closely adjacent pins. In a first embodiment, an optimal boundary-scan test pattern is generated. In a second embodiment, boundary-scan test diagnosis is enhanced by utilizing x,y coordinate data corresponding to the physical location of devices on the tested circuit. In a third embodiment, diagnosis of unpowered short-circuit testing is enhanced.

Abstract: A method for testing a circuit board having both boundary-scan and non-boundary-scan devices is provided. The test method distinguishes boundary-scan nodes from non-boundary-scan nodes and uses cartesian coordinates (X,Y) of every pin of every device on the circuit board to determine a number of sets of non-boundary-scan nodes that are within a predetermined distance "R" from a device pin coupled to a boundary-scan node. The number of sets of non-boundary-scan nodes are grouped into "independent" groups which can be tested in parallel. A test cycle is performed by testing independent non-boundary-scan nodes in parallel by forcing drivers in the boundary-scan devices to a first logic state, and forcing each of the non-boundary-scan nodes to another logic state for a brief interval. Receivers on the boundary-scan devices capture a response vector during the brief interval, which is scanned out of the circuit board for evaluation.

Abstract: A method for testing a circuit board having both boundary-scan and non-boundary-scan devices is provided. The test method distinguishes boundary-scan nodes from non-boundary-scan nodes and uses cartesian coordinates (X,Y) of every pin of every device on the circuit board to determine a number of sets of non-boundary-scan nodes that are within a predetermined distance "R" from a device pin coupled to a boundary-scan node. The number of sets of non-boundary-scan nodes are grouped into "independent" groups which can be tested in parallel. A test cycle is performed by testing independent non-boundary-scan nodes in parallel by forcing drivers in the boundary-scan devices to a first logic state, and forcing each of the non-boundary-scan nodes to another logic state for a brief interval. Receivers on the boundary-scan devices capture a response vector during the brief interval, which is scanned out of the circuit board for evaluation.

Abstract: Test connectors connect a circuit tester to an electronic device to be tested. The test vector matrix is divided into segments, each segment including one or more columns of the matrix. The unique vector segments within each matrix segment are stored in RAMs, one RAM for each test connector. A driver/comparator applies an electrical signal to some of the test connectors in response to a signal received from its associated RAM and receives an electrical signal on other of the test connectors and compares it to a signal received from the RAM. There is an independent sequencer for each matrix segment, each sequencer addressing the RAMs for that segment. A clock initiates and clocks the sequencers in synchrony to produce the test on the test connectors from the unique test vector segments stored in the RAMs.

Abstract: The (X,Y) positions of the nodes in a circuit containing boundary scan components and non-boundary-scan components are stored in a computer. The computer selects a set of non-boundary scan nodes within a radius R of a selected boundary-scan node, R being the length of solder bridges in the circuit. A logic 0 voltage is applied to the set and a boundary-scan test is performed. If the boundary-scan test fails, a fault is declared in the circuit between the set and the selected boundary-scan node. A logic 1 voltage is applied to one of the nodes in the set, and the test repeated. If the test returns different results, the fault is declared between that one node and the selected boundary-scan node. A time limit is established for each non-boundary scan node corresponding to the length of time a short in that node can be tolerated. The boundary-scan nodes in the circuit are tested in the order of ascending time limits in its associated set.

Abstract: A partitioned boundary-scan interconnect test method for loaded printed wiring boards (PWB's) is disclosed which reduces testing-induced damage to electronic components. The method is adapted to expeditiously identify all short-circuits on a PWB. The partitioned boundary-scan interconnect test includes four sub-tests. A powered shorts boundary-scan sub-test searches for short-circuit faults between conventional nets and boundary-scan nets. A boundary-scan interconnect shorts sub-test searches for short-circuits between boundary-scan nets. The boundary-scan interconnect shorts sub-test is optimized by testing a single driver on each net. All other drivers are tested during a boundary-scan bus-wire sub-test. A boundary-scan in-circuit sub-test checks the connectivity of boundary-scan devices in partial boundary-scan nets (i.e., nets having a driver or receiver but not both). By partitioning the boundary-scan interconnect test into these sub-tests, the potential for testing-induced damage is reduced.

Abstract: The (X,Y) positions of the nodes in a circuit containing boundary scan components and non-boundary scan components are stored in a computer. The computer selects a set of non-boundary scan nodes within a radius R of a selected boundary-scan node, R being the length of solder bridges in the circuit. A logic 0 voltage is applied to the set and a boundary-scan test is performed. If the boundary-scan test fails, a fault is declared in the circuit between the set and the selected boundary-scan node. A logic 1 voltage is applied to one of the nodes in the set, and the test repeated. If the test returns different results, the fault is declared between that one node and the selected boundary-scan node. A time limit is established for each non-boundary scan node corresponding to the length of time a short in that node can be tolerated. The boundary-scan nodes in the circuit are tested in the order of ascending time limits in its associated set.