Abstract: Forming a packaged device having a semiconductor device having a first major surface and a second major surface includes forming an encapsulating layer over the second major surface of the semiconductor device and around sides of the semiconductor device and leaving the first major surface of the first semiconductor device exposed. An insulating layer is formed over the first major surface. A via is formed in the insulating layer. A tangible element is coupled to the semiconductor device through the via. At least a portion of the tangible element is surrounded with a cavity wall having a first face toward the element and a second face away from the element. A supporting layer, after surrounding the tangible element, is formed over the insulating layer so that the supporting layer is adjacent to the second face and blocked from the first face thereby providing protection for the tangible element.

Abstract: A method of forming a semiconductor package includes providing a carrier, attaching a first surface of a first device on the carrier, wherein the first surface comprises a first active surface of the first device, and attaching a second surface of a second device on the carrier. In one embodiment, the second surface is opposite a third surface of the second semiconductor die and the third surface comprises a second active surface. A first insulating material can be formed between the first device and the second device.

Abstract: In one form a device having an integrated circuit is rendered useless by providing a piezo element coupled to a voltage terminal of the integrated circuit of the device. A render useless signal is generated by any of several ways. The piezo element, in response to the render useless signal, renders in any one of several ways the device to be rendered useless. The piezo element, when disturbed, generates a voltage which is provided to the voltage terminal of the integrated circuit, the voltage being sufficiently high to render useless at least a portion of the integrated circuit. In other forms the render useless signal renders MRAM circuitry within the device useless by moving a magnetic field across the MRAM circuitry to vary resistance of memory reference cells. In one form the magnetic field is moved by spring-loading or pivoting a magnet that is released by the piezo element.

Abstract: A method of packaging a first device having a first major surface and a second major surface includes forming a first layer over a second major surface of the first device and around sides of the first device and leaving the first major surface of the first device exposed, wherein the first layer is selected from the group consisting of an encapsulant and a polymer; forming a first dielectric layer over the first major surface of the first device, forming a via in the first dielectric layer, forming a seed layer within the via and over a portion of the first dielectric layer, physically coupling a connector to the seed layer, and plating a conductive material over the seed layer to form a first interconnect in the first via and over a portion of the first dielectric layer.

Abstract: Electromagnetic shielding for an integrated circuit packaged device. The method includes forming shielding structures by forming openings in an encapsulated structure. The openings are filled with conductive material that surrounds at least one die. The encapsulated structure may include a plurality of integrated circuit die. A layered redistribution structure is formed on one side of the encapsulated structure.

Abstract: A device under test (DUT) is tested via a test interposer. The test interposer includes a first set of contacts at a first surface to interface with the contacts of a load board or other interface of an automated test equipment (ATE) and a second set of contacts at an opposing second surface to interface with the contacts of the DUT. The second set of contacts can have a smaller contact pitch than the contact pitch of the first set of contacts to facilitate connection to the smaller pitch of the contacts of the DUT. The test interposer further includes one or more active circuit components or passive circuit components to facilitate testing of the DUT. The test interposer can be implemented as an integrated circuit (IC) package that encapsulates the circuit components.

Abstract: A method of packaging a first device having a first major surface and a second major surface includes forming a first layer over a second major surface of the first device and around sides of the first device and leaving the first major surface of the first device exposed, wherein the first layer is selected from the group consisting of an encapsulant and a polymer; forming a first dielectric layer over the first major surface of the first device, forming a via in the first dielectric layer, forming a seed layer within the via and over a portion of the first dielectric layer, physically coupling a connector to the seed layer, and plating a conductive material over the seed layer to form a first interconnect in the first via and over a portion of the first dielectric layer.

Abstract: A Schmitt trigger has a first inverter, a second inverter, a bias means, and a transistor. The inverter has an input and an output. The second inverter has an input coupled to the output of the first inverter and has an output. The bias means provides a first bias voltage on a first output terminal. A magnitude of the bias voltage is selectable by a first input signal. The transistor has a first current electrode coupled to a first power supply terminal, a control electrode coupled to the output of the second inverter, a second current electrode coupled to the output of the first inverter, and a body coupled to the first output terminal. Selectability of the magnitude of the bias voltage provides selectability of the hysteresis of the Schmitt trigger.

Abstract: A method of packaging a first device having a first major surface and a second major surface includes forming a first layer over a second major surface of the first device and around sides of the first device and leaving the first major surface of the first device exposed, wherein the first layer is selected from the group consisting of an encapsulant and a polymer; forming a first dielectric layer over the first major surface of the first device, forming a via in the first dielectric layer, forming a seed layer within the via and over a portion of the first dielectric layer, physically coupling a connector to the seed layer, and plating a conductive material over the seed layer to form a first interconnect in the first via and over a portion of the first dielectric layer.

Abstract: Electromagnetic shielding for an integrated circuit packaged device. The method includes forming shielding structures by forming openings in an encapsulated structure. The openings are filled with conductive material that surrounds at least one die. The encapsulated structure may include a plurality of integrated circuit die. A layered redistribution structure is formed on one side of the encapsulated structure.

Abstract: A method is for packaging a first device having a first major surface and a second major surface. An encapsulant is formed over a second major surface of the first device and around sides of the first device. This leaves the first major surface of the first device exposed. A first dielectric layer is formed over the first major surface of the first device. a side contact interface is formed having at least a portion over the first dielectric layer. The encapsulant is cut to form a plurality of sides of encapsulant. A portion of the encapsulant is removed along a first side of the plurality of sides to expose a portion of the side contact interface along the first side of the plurality of sides.

Abstract: A packaged device has a semiconductor device that has a first major surface and a second major surface. An encapsulating layer is formed over the second major surface and around sides of the semiconductor device. The first major surface of the semiconductor device is left exposed. The semiconductor device has the ability to perform a keypad function and has a first contact that has a surface that is external to the semiconductor device. The first contact is used in performing the keypad function. A first dielectric layer is formed over the first major surface. A second dielectric layer is formed over the second major surface. A second contact that has a surface that is external to the packaged device is connected to the first contact. A keypad can be connected to the second contact. The number of such first and second contacts is variable based on the keypad.

Abstract: A method is for packaging a first device having a first major surface and a second major surface. An encapsulant is formed over a second major surface of the first device and around sides of the first device. This leaves the first major surface of the first device exposed. A first dielectric layer is formed over the first major surface of the first device. a side contact interface is formed having at least a portion over the first dielectric layer. The encapsulant is cut to form a plurality of sides of encapsulant. A portion of the encapsulant is removed along a first side of the plurality of sides to expose a portion of the side contact interface along the first side of the plurality of sides.

Abstract: A method of packaging a first device having a first major surface and a second major surface includes forming a first layer over a second major surface of the first device and around sides of the first device and leaving the first major surface of the first device exposed, wherein the first layer is selected from the group consisting of an encapsulant and a polymer; forming a first dielectric layer over the first major surface of the first device, forming a via in the first dielectric layer, forming a seed layer within the via and over a portion of the first dielectric layer, physically coupling a connector to the seed layer, and plating a conductive material over the seed layer to form a first interconnect in the first via and over a portion of the first dielectric layer.

Abstract: Forming a packaged device having a semiconductor device having a first major surface and a second major surface includes forming an encapsulating layer over the second major surface of the semiconductor device and around sides of the semiconductor device and leaving the first major surface of the first semiconductor device exposed. An insulating layer is formed over the first major surface. A via is formed in the insulating layer. A tangible element is coupled to the semiconductor device through the via. At least a portion of the tangible element is surrounded with a cavity wall having a first face toward the element and a second face away from the element. A supporting layer, after surrounding the tangible element, is formed over the insulating layer so that the supporting layer is adjacent to the second face and blocked from the first face thereby providing protection for the tangible element.

Abstract: Forming a packaged device having a semiconductor device having a first major surface and a second major surface includes forming an encapsulating layer over the second major surface of the semiconductor device and around sides of the semiconductor device and leaving the first major surface of the first semiconductor device exposed. A first insulating layer is formed over the first major surface. A plurality of vias are formed in the first insulating layer. A plurality of contacts are formed to the semiconductor device through the first plurality of vias, wherein each of the plurality of contacts has a surface above the first insulating layer. A supporting layer is formed over the first insulating layer leaving an opening over the first plurality of contacts wherein the opening has a sidewall surrounding the plurality of contacts.

Abstract: A variable switching point inverter (30) is disclosed which lowers the threshold voltage lowered for both rising and falling edge input voltages (VIN) by changing the P/N ratio of the inverter based on the delayed output state (VOUT) of the inverter. The variable switching point inverter may be constructed as a CMOS integrated circuit with a first inverter stage (33, 34) coupled in parallel to a second inverter stage (35, 36) having extra PMOS (37) and NMOS (38) transistors connected to VDD and VSS, respectively, where the extra PMOS and NMOS transistors are controlled by the delayed output signal (40) generated by a delay element (39) coupled to the output of the first inverter stage. By using a delayed feed back signal (40) to control the extra PMOS and NMOS gates (37, 38), the switching point voltage of the first inverter stage (33, 34) is altered, depending on whether the input transitions are high-to-low or low-to-high.

Abstract: Apparatus and methods are described for a background microcontroller debugger. A method to debug a microcontroller includes sending a three level signal from a debug module, receiving the three level signal at a single pin on an MCU, sending a second three level signal from the single pin on the MCU, and receiving the second three level signal at the debug module. An apparatus to debug a microcontroller includes a tri-statable pad driver to transmit a three level signal, a reference voltage divider coupled to the tri-statable pad diver, a plurality of voltage comparators to receive the three level signal, a resistive voltage divider to maintain thresholds for the plurality of voltage comparators, and a plurality of logic elements coupled to the plurality of voltage comparators to receive the three level signal.

Abstract: Wafer level testing is accomplished by using a visual indicator (43) in lieu of a probe machine. Before singulation, each die (52) in a wafer (50) is placed into a test mode and BIST circuitry (39) in each die performs predetermined tests of the other circuits on the die. A pass/fail signal is communicated to a visual indicating device, such as an LED, on the wafer. Each die has a corresponding visual indicator. The LED may be contained either on the die or in the scribe area. Multiple LEDs may be used for multiple circuit modules under test. The test permits easy detection of failures without using probing. Testing such as burn-in may be performed to determine whether a part will survive a range of operating conditions. In one form, a CMOS implementation of an LED may be used in conjunction with a CMOS wafer.

Abstract: Apparatus and methods are described for a background microcontroller debugger. A method to debug a microcontroller includes sending a three level signal from a debug module, receiving the three level signal at a single pin on an MCU, sending a second three level signal from the single pin on the MCU, and receiving the second three level signal at the debug module. An apparatus to debug a microcontroller includes a tri-statable pad driver to transmit a three level signal, a reference voltage divider coupled to the tri-statable pad diver, a plurality of voltage comparators to receive the three level signal, a resistive voltage divider to maintain thresholds for the plurality of voltage comparators, and a plurality of logic elements coupled to the plurality of voltage comparators to receive the three level signal.