Abstract: A method and system for characterizing and validating the timing of LVS circuits. In particular, based upon an input of a topological description of an LVS circuit (e.g., a netlist) and other circuit parameters such as a clock specification or any mutex or logical correlations between inputs and ignored devices, an output of all paths and arcs from primary inputs to sense amplifier inputs is generated. A complete set of valid input vectors required to exercise all paths is generated. These vectors may then be exhaustively simulated to provide input waveforms to all sense amplifiers.

Abstract: A method and system for characterizing and validating the timing of LVS circuits. In particular, based upon an input of a topological description of an LVS circuit (e.g., a netlist) and other circuit parameters such as a clock specification or any mutex or logical correlations between inputs and ignored devices, an output of all paths and arcs from primary inputs to sense amplifier inputs is generated. A complete set of valid input vectors required to exercise all paths is generated. These vectors may then be exhaustively simulated to provide input waveforms to all sense amplifiers.

Abstract: A system and method of synthesizing and/or verifying a circuit from a behavioral description of that circuit. A signal ordering of signals in the circuit is defined, wherein defining a signal ordering of signals in the circuit includes specifying a relative ordering of a plurality of events within the circuit. The behavioral description is modified as a function of the signal ordering. The circuit is then synthesized and/or verified as a function of the modified behavioral description.

Abstract: A communication network formed by a plurality of communication processors which are connected together in hexagonal array is disclosed. The data processing system consists of a plurality of data processors. Each data processor is coupled to a communication processor which is responsible for sending messages to and receiving messages from other communication processors. Each communication processor communicates with the 6 communication processors adjacent to it through 6 ports. When a given data processor wishes to send a message to another data processor, it transfers the message to its communication processor which in turn transfers the message to the communication processor coupled to one of these 6 ports with information specifying the final destination of the message. The message routing algorithm used by each of communication processors automatically reroutes messages around communication bottlenecks created by a malfunctioning communication processor or by a local communication overload.