Patents by Inventor Kenneth W. Marr
Kenneth W. Marr has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 11966303Abstract: Exemplary methods, apparatuses, and systems including memory self-recovery management to correct failures due to soft-error rate events. The self-recovery manager detects a failure of a memory device. The self-recovery manager retrieves a set of register values from the memory device. The self-recovery manager stores the set of register values from the memory device. The self-recovery manager issues a reset command to the memory device, the reset command including generating a re-initialized set of register values. The self-recovery manager compares the set of register values with the re-initialized set of register values. The self-recovery manager triggering a self-recovery attempt using the comparison of the set of register values with the re-initialized set of register values.Type: GrantFiled: July 29, 2022Date of Patent: April 23, 2024Assignee: MICRON TECHNOLOGY, INC.Inventors: Robert Mason, Scott A. Stoller, Pitamber Shukla, Kenneth W. Marr, Chi Ming Chu, Hossein Afkhami
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Publication number: 20240071516Abstract: A discharge circuit includes a transistor and a metal resistor connected to the transistor. The transistor includes a plurality of unit cells. The metal resistor includes a plurality of resistor portions corresponding to the plurality of unit cells. Each unit cell of the plurality of unit cells has a footprint and a corresponding resistor portion of the plurality of resistor portions is arranged within the footprint.Type: ApplicationFiled: August 29, 2022Publication date: February 29, 2024Applicant: MICRON TECHNOLOGY, INC.Inventors: Kenneth W. Marr, James E. Davis, Chiara Cerafogli
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Publication number: 20230393955Abstract: Exemplary methods, apparatuses, and systems including memory self-recovery management to correct failures due to soft-error rate events. The self-recovery manager detects a failure of a memory device. The self-recovery manager retrieves a set of register values from the memory device. The self-recovery manager stores the set of register values from the memory device. The self-recovery manager issues a reset command to the memory device, the reset command including generating a re-initialized set of register values. The self-recovery manager compares the set of register values with the re-initialized set of register values. The self-recovery manager triggering a self-recovery attempt using the comparison of the set of register values with the re-initialized set of register values.Type: ApplicationFiled: July 29, 2022Publication date: December 7, 2023Inventors: Robert Mason, Scott A. Stoller, Pitamber Shukla, Kenneth W. Marr, Chi Ming Chu, Hossein Afkhami
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Patent number: 11823731Abstract: Devices are disclosed. A device may include a source configured to couple to a number of memory cells. The device may also include at least one transistor coupled between the source and a ground voltage. Further, the device may include an antifuse coupled between the at least one transistor and the ground voltage. Methods and systems are also disclosed.Type: GrantFiled: September 27, 2021Date of Patent: November 21, 2023Assignee: Micron Technology, Inc.Inventors: Kenneth W. Marr, Michael A. Smith
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Publication number: 20230275042Abstract: Active protection circuits for semiconductor devices, and associated systems and methods, are disclosed herein. The active protection circuits may protect various components of the semiconductor devices from process induced damage—e.g., stemming from process charging effects. In some embodiments, the active protection circuit includes an FET and a resistor coupled to certain nodes (e.g., source plates for 3D NAND memory arrays) of the semiconductor devices, which may be prone to accumulate the process charging effects. The active protection circuits prevent the nodes from reaching a predetermined voltage during process steps utilizing charged particles. Subsequently, metal jumpers may be added to the active protection circuits to deactivate the FETs for normal operations of the semiconductor devices. Further, the FET and the resistor of the active protection circuit may be integrated with an existing component of the semiconductor device.Type: ApplicationFiled: May 3, 2023Publication date: August 31, 2023Inventors: Michael A. Smith, Kenneth W. Marr
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Patent number: 11676917Abstract: Active protection circuits for semiconductor devices, and associated systems and methods, are disclosed herein. The active protection circuits may protect various components of the semiconductor devices from process induced damage—e.g., stemming from process charging effects. In some embodiments, the active protection circuit includes an FET and a resistor coupled to certain nodes (e.g., source plates for 3D NAND memory arrays) of the semiconductor devices, which may be prone to accumulate the process charging effects. The active protection circuits prevent the nodes from reaching a predetermined voltage during process steps utilizing charged particles. Subsequently, metal jumpers may be added to the active protection circuits to deactivate the FETs for normal operations of the semiconductor devices. Further, the FET and the resistor of the active protection circuit may be integrated with an existing component of the semiconductor device.Type: GrantFiled: November 24, 2020Date of Patent: June 13, 2023Assignee: Micron Technology, Inc.Inventors: Michael A. Smith, Kenneth W. Marr
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Publication number: 20220165688Abstract: Active protection circuits for semiconductor devices, and associated systems and methods, are disclosed herein. The active protection circuits may protect various components of the semiconductor devices from process induced damage—e.g., stemming from process charging effects. In some embodiments, the active protection circuit includes an FET and a resistor coupled to certain nodes (e.g., source plates for 3D NAND memory arrays) of the semiconductor devices, which may be prone to accumulate the process charging effects. The active protection circuits prevent the nodes from reaching a predetermined voltage during process steps utilizing charged particles. Subsequently, metal jumpers may be added to the active protection circuits to deactivate the FETs for normal operations of the semiconductor devices. Further, the FET and the resistor of the active protection circuit may be integrated with an existing component of the semiconductor device.Type: ApplicationFiled: November 24, 2020Publication date: May 26, 2022Inventors: Michael A. Smith, Kenneth W. Marr
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Publication number: 20220013160Abstract: Devices are disclosed. A device may include a source configured to couple to a number of memory cells. The device may also include at least one transistor coupled between the source and a ground voltage. Further, the device may include an antifuse coupled between the at least one transistor and the ground voltage. Methods and systems are also disclosed.Type: ApplicationFiled: September 27, 2021Publication date: January 13, 2022Inventors: Kenneth W. Marr, Michael A. Smith
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Publication number: 20210407989Abstract: Methods of forming a circuit-protection device include forming a dielectric having a first thickness and a second thickness greater than the first thickness over a semiconductor, forming a conductor over the dielectric, and patterning the conductor to retain a portion of the conductor over a portion of the dielectric having the second thickness, and to retain substantially no portion of the conductor over a portion of the dielectric having the first thickness, wherein the retained portion of the conductor defines a control gate of a field-effect transistor of the circuit-protection device.Type: ApplicationFiled: September 13, 2021Publication date: December 30, 2021Applicant: MICRON TECHNOLOGY, INC.Inventors: Michael A. Smith, Kenneth W. Marr
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Patent number: 11158367Abstract: Memory devices are disclosed. A memory device may include a source (SRC) plate configured to couple to a number of memory cells. The memory device may also include a resistor coupled between the source plate and a node. Further, the memory device may include at least one transistor coupled between the source plate and the ground voltage, wherein a gate of the at least one transistor is coupled to the node. The transistor may be configured to couple the SRC plate to the ground voltage during a processing stage. The transistor may further be configured to isolate the SRC plate from the ground voltage during an operation stage. Methods and electronic systems are also disclosed.Type: GrantFiled: April 10, 2020Date of Patent: October 26, 2021Assignee: Micron Technology, Inc.Inventors: Kenneth W. Marr, Michael A. Smith
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Publication number: 20210319827Abstract: Memory devices are disclosed. A memory device may include a source (SRC) plate configured to couple to a number of memory cells. The memory device may also include a resistor coupled between the source plate and a node. Further, the memory device may include at least one transistor coupled between the source plate and the ground voltage, wherein a gate of the at least one transistor is coupled to the node. The transistor may be configured to couple the SRC plate to the ground voltage during a processing stage. The transistor may further be configured to isolate the SRC plate from the ground voltage during an operation stage. Methods and electronic systems are also disclosed.Type: ApplicationFiled: April 10, 2020Publication date: October 14, 2021Inventors: Kenneth W. Marr, Michael A. Smith
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Patent number: 11139289Abstract: Methods of forming a circuit-protection device include forming a dielectric having a first thickness and a second thickness greater than the first thickness over a semiconductor, forming a conductor over the dielectric, and patterning the conductor to retain a portion of the conductor over a portion of the dielectric having the second thickness, and to retain substantially no portion of the conductor over a portion of the dielectric having the first thickness, wherein the retained portion of the conductor defines a control gate of a field-effect transistor of the circuit-protection device, as well as apparatus having such circuit-protection devices.Type: GrantFiled: August 19, 2019Date of Patent: October 5, 2021Assignee: Micron Technology, Inc.Inventors: Michael A. Smith, Kenneth W. Marr
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Patent number: 10665307Abstract: Memory devices include an array of memory cells and circuitry for control and/or access of the array of memory cells, wherein the circuitry is configured to perform a method including applying a first voltage to the access line following a verify of the program operation then electrically floating the access line, connecting the access line to the first input of the operational amplifier, applying a second voltage to a second access line adjacent the access line, applying a reference current to the access line while applying the second voltage to the second access line, applying the reference voltage to the second input of the operational amplifier while applying the second voltage to the second access line, and indicating a fail status of the program operation if current flow to or from the access line exceeds the reference current sinking current from, or sourcing current to, respectively, the first access line.Type: GrantFiled: June 5, 2019Date of Patent: May 26, 2020Assignee: Micron Technology, Inc.Inventors: Jeffrey A. Kessenich, Joemar Sinipete, Chiming Chu, Jason L. Nevill, Kenneth W. Marr, Renato C. Padilla
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Patent number: 10580766Abstract: Methods of forming a circuit-protection device include forming a dielectric having a first thickness and a second thickness greater than the first thickness over a semiconductor, forming a conductor over the dielectric, and patterning the conductor to retain a portion of the conductor over a portion of the dielectric having the second thickness, and to retain substantially no portion of the conductor over a portion of the dielectric having the first thickness, wherein the retained portion of the conductor defines a control gate of a field-effect transistor of the circuit-protection device.Type: GrantFiled: August 19, 2019Date of Patent: March 3, 2020Assignee: Micron Technology, Inc.Inventors: Michael A. Smith, Kenneth W. Marr
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Publication number: 20190371790Abstract: Methods of forming a circuit-protection device include forming a dielectric having a first thickness and a second thickness greater than the first thickness over a semiconductor, forming a conductor over the dielectric, and patterning the conductor to retain a portion of the conductor over a portion of the dielectric having the second thickness, and to retain substantially no portion of the conductor over a portion of the dielectric having the first thickness, wherein the retained portion of the conductor defines a control gate of a field-effect transistor of the circuit-protection device, as well as apparatus having such circuit-protection devices.Type: ApplicationFiled: August 19, 2019Publication date: December 5, 2019Applicant: MICRON TECHNOLOGY, INC.Inventors: Michael A. Smith, Kenneth W. Marr
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Publication number: 20190371789Abstract: Methods of forming a circuit-protection device include forming a dielectric having a first thickness and a second thickness greater than the first thickness over a semiconductor, forming a conductor over the dielectric, and patterning the conductor to retain a portion of the conductor over a portion of the dielectric having the second thickness, and to retain substantially no portion of the conductor over a portion of the dielectric having the first thickness, wherein the retained portion of the conductor defines a control gate of a field-effect transistor of the circuit-protection device.Type: ApplicationFiled: August 19, 2019Publication date: December 5, 2019Applicant: MICRON TECHNOLOGY, INC.Inventors: Michael A. Smith, Kenneth W. Marr
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Patent number: 10431577Abstract: Methods of forming a circuit-protection device include forming a dielectric having a first thickness and a second thickness greater than the first thickness over a semiconductor, forming a conductor over the dielectric, and patterning the conductor to retain a portion of the conductor over a portion of the dielectric having the second thickness, and to retain substantially no portion of the conductor over a portion of the dielectric having the first thickness, wherein the retained portion of the conductor defines a control gate of a field-effect transistor of the circuit-protection device.Type: GrantFiled: February 9, 2018Date of Patent: October 1, 2019Assignee: Micron Technology, Inc.Inventors: Michael A. Smith, Kenneth W. Marr
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Publication number: 20190287634Abstract: Memory devices include an array of memory cells and circuitry for control and/or access of the array of memory cells, wherein the circuitry is configured to perform a method including applying a first voltage to the access line following a verify of the program operation then electrically floating the access line, connecting the access line to the first input of the operational amplifier, applying a second voltage to a second access line adjacent the access line, applying a reference current to the access line while applying the second voltage to the second access line, applying the reference voltage to the second input of the operational amplifier while applying the second voltage to the second access line, and indicating a fail status of the program operation if current flow to or from the access line exceeds the reference current sinking current from, or sourcing current to, respectively, the first access line.Type: ApplicationFiled: June 5, 2019Publication date: September 19, 2019Applicant: MICRON TECHNOLOGY, INC.Inventors: Jeffrey A. Kessenich, Joemar Sinipete, Chiming Chu, Jason L. Nevill, Kenneth W. Marr, Renato C. Padilla
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Patent number: 10366767Abstract: Memory devices include an array of memory cells and circuitry for control and/or access of the array of memory cells, wherein the circuitry is configured to perform a method including applying a particular voltage to an unselected access line of a program operation, sensing a current of a selected access line of the program operation while applying the particular voltage to the unselected access line, indicating a fail status of the program operation if an absolute value of the sensed current of the selected access line is greater than a particular current, and proceeding with the program operation if the absolute value of the sensed current of the selected access line is less than a particular current.Type: GrantFiled: August 25, 2017Date of Patent: July 30, 2019Assignee: Micron Technology, Inc.Inventors: Jeffrey A. Kessenich, Joemar Sinipete, Chiming Chu, Jason L. Nevill, Kenneth W. Marr, Renato C. Padilla
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Publication number: 20190206856Abstract: Methods of forming a circuit-protection device include forming a dielectric having a first thickness and a second thickness greater than the first thickness over a semiconductor, forming a conductor over the dielectric, and patterning the conductor to retain a portion of the conductor over a portion of the dielectric having the second thickness, and to retain substantially no portion of the conductor over a portion of the dielectric having the first thickness, wherein the retained portion of the conductor defines a control gate of a field-effect transistor of the circuit-protection device.Type: ApplicationFiled: February 9, 2018Publication date: July 4, 2019Applicant: MICRON TECHNOLOGY, INC.Inventors: Michael A. Smith, Kenneth W. Marr