Patents by Inventor Kenneth W. Marr
Kenneth W. Marr has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20170352431Abstract: Memory devices include an array of memory cells and circuitry for control and/or access of the array of memory cells, wherein the circuitry is configured to perform a method including applying a particular voltage to an unselected access line of a program operation, sensing a current of a selected access line of the program operation while applying the particular voltage to the unselected access line, indicating a fail status of the program operation if an absolute value of the sensed current of the selected access line is greater than a particular current, and proceeding with the program operation if the absolute value of the sensed current of the selected access line is less than a particular current.Type: ApplicationFiled: August 25, 2017Publication date: December 7, 2017Applicant: MICRON TECHNOLOGY, INC.Inventors: Jeffrey A. Kessenich, Joemar Sinipete, Chiming Chu, Jason L. Nevill, Kenneth W. Marr, Renato C. Padilla
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Patent number: 9761322Abstract: Methods of operating a memory device having embedded leak checks may mitigate data loss events due to access line defects, and may facilitate improved power consumption characteristics. Such methods might include applying a program pulse to a selected access line coupled to a memory cell selected for programming, verifying whether the selected memory cell has reached a desired data state, bringing the selected access line to a first voltage, applying a second voltage to an unselected access line, applying a reference current to the selected access line, and determining if a current flow between the selected access line and the unselected access line is greater than the reference current.Type: GrantFiled: February 9, 2016Date of Patent: September 12, 2017Assignee: Micron Technology, Inc.Inventors: Jeffery A. Kessenich, Joemar Sinipete, Chiming Chu, Jason L. Nevill, Kenneth W. Marr, Renato C. Padilla
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Patent number: 9557376Abstract: Apparatuses and methods can include a die seal between an integrated circuit region of a die and a periphery of the die. A via chain(s) may be arranged around an inner circumference of the die seal between the die seal and the integrated circuit region and/or around an outer circumference of the die seal between the die seal and the periphery of the die. The via chain may include a plurality of contacts comprised of conductive material and extending through portions of the die. Circuitry may be coupled to an end of the via chain to detect an electrical signal. Additional apparatuses and methods are described.Type: GrantFiled: March 14, 2016Date of Patent: January 31, 2017Assignee: Micron Technology, Inc.Inventors: Charles H. Dennison, Kenneth W. Marr, Deepak Thimmegowda, Philip J. Ireland
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Publication number: 20160195581Abstract: Apparatuses and methods can include a die seal between an integrated circuit region of a die and a periphery of the die. A via chain(s) may be arranged around an inner circumference of the die seal between the die seal and the integrated circuit region and/or around an outer circumference of the die seal between the die seal and the periphery of the die. The via chain may include a plurality of contacts comprised of conductive material and extending through portions of the die. Circuitry may be coupled to an end of the via chain to detect an electrical signal. Additional apparatuses and methods are described.Type: ApplicationFiled: March 14, 2016Publication date: July 7, 2016Inventors: Charles H. Dennison, Kenneth W. Marr, Deepak Thimmegowda, Philip J. Ireland
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Publication number: 20160155513Abstract: Methods of operating a memory device having embedded leak checks may mitigate data loss events due to access line defects, and may facilitate improved power consumption characteristics. Such methods might include applying a program pulse to a selected access line coupled to a memory cell selected for programming, verifying whether the selected memory cell has reached a desired data state, bringing the selected access line to a first voltage, applying a second voltage to an unselected access line, applying a reference current to the selected access line, and determining if a current flow between the selected access line and the unselected access line is greater than the reference current.Type: ApplicationFiled: February 9, 2016Publication date: June 2, 2016Applicant: MICRON TECHNOLOGY, INC.Inventors: Jeffery A. Kessenich, Joemar Sinipete, Chiming Chu, Jason L. Nevill, Kenneth W. Marr, Renato C. Padilla
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Patent number: 9287184Abstract: Apparatuses and methods can include a die seal between an integrated circuit region of a die and a periphery of the die. A via chain(s) may be arranged around an inner circumference of the die seal between the die seal and the integrated circuit region and/or around an outer circumference of the die seal between the die seal and the periphery of the die. The via chain may include a plurality of contacts comprised of conductive material and extending through portions of the die. Circuitry may be coupled to an end of the via chain to detect an electrical signal. Additional apparatuses and methods are described.Type: GrantFiled: December 13, 2013Date of Patent: March 15, 2016Assignee: Micron Technology, Inc.Inventors: Charles H. Dennison, Kenneth W. Marr, Deepak Thimmegowda, Philip J. Ireland
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Patent number: 9281078Abstract: Methods of operating a memory device having embedded leak checks may mitigate data loss events due to access line defects, and may facilitate improved power consumption characteristics. Such methods might include applying a program pulse to a selected access line coupled to a memory cell selected for programming, verifying whether the selected memory cell has reached a desired data state, bringing the selected access line to a first voltage, applying a second voltage to an unselected access line, applying a reference current to the selected access line, and determining if a current flow between the selected access line and the unselected access line is greater than the reference current.Type: GrantFiled: June 12, 2014Date of Patent: March 8, 2016Assignee: Micron Technology, Inc.Inventors: Jeffrey A. Kessenich, Joemar Sinipete, Chiming Chu, Jason L. Nevill, Kenneth W. Marr, Renato C. Padilla
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Publication number: 20150364213Abstract: Methods of operating a memory device having embedded leak checks may mitigate data loss events due to access line defects, and may facilitate improved power consumption characteristics. Such methods might include applying a program pulse to a selected access line coupled to a memory cell selected for programming, verifying whether the selected memory cell has reached a desired data state, bringing the selected access line to a first voltage, applying a second voltage to an unselected access line, applying a reference current to the selected access line, and determining if a current flow between the selected access line and the unselected access line is greater than the reference current.Type: ApplicationFiled: June 12, 2014Publication date: December 17, 2015Applicant: Micron Technology, Inc.Inventors: Jeffrey A. Kessenich, Joemar Sinipete, Chiming Chu, Jason L. Nevill, Kenneth W. Marr, Renato C. Padilla
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Publication number: 20150170979Abstract: Apparatuses and methods can include a die seal between an integrated circuit region of a die and a periphery of the die. A via chain(s) may be arranged around an inner circumference of the die seal between the die seal and the integrated circuit region and/or around an outer circumference of the die seal between the die seal and the periphery of the die. The via chain may include a plurality of contacts comprised of conductive material and extending through portions of the die. Circuitry may be coupled to an end of the via chain to detect an electrical signal. Additional apparatuses and methods are described.Type: ApplicationFiled: December 13, 2013Publication date: June 18, 2015Applicant: Micron Technology, Inc.Inventors: Charles H. Dennison, Kenneth W. Marr, Deepak Thimmegowda, Philip J. Ireland
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Patent number: 7873882Abstract: Some embodiments of the invention include a memory device has a number of memory segments connected to a supply source through a supply control circuit. The supply control circuit isolates a selected memory segment from the supply source when the selected memory segment is defective. The memory device replaces a defective memory segment with a redundant segment. Other embodiments are described and claimed.Type: GrantFiled: July 25, 2006Date of Patent: January 18, 2011Assignee: Micron Technology, Inc.Inventor: Kenneth W. Marr
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Patent number: 7836362Abstract: Some embodiments of the invention include a memory device has a number of memory segments connected to a supply source through a supply control circuit. The supply control circuit isolates a selected memory segment from the supply source when the selected memory segment is defective. The memory device replaces a defective memory segment with a redundant segment. Other embodiments are described and claimed.Type: GrantFiled: July 25, 2006Date of Patent: November 16, 2010Assignee: Micron Technology, Inc.Inventor: Kenneth W. Marr
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Patent number: 7437632Abstract: A memory device has a number of memory segments connected to a supply source through a supply control circuit. If one of the memory segments is defective, the supply control circuit isolates the defective memory segment from the supply source. The memory device replaces the defective memory segment with a redundant segment.Type: GrantFiled: June 24, 2003Date of Patent: October 14, 2008Assignee: Micron Technology, Inc.Inventor: Kenneth W. Marr
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Patent number: 7425472Abstract: A fuse for use in a semiconductor device includes spaced-apart terminals with at least two layers of conductive material and a single-layer conductive link joining the spaced-apart terminals and including a single layer of conductive material. A first, lower layer of the terminals of each fuse may be formed from conductively doped polysilicon. The second, upper layer of each fuse terminal may be formed from a polycide, a metal silicide, a metal, or a conductive alloy. The conductive link of each fuse may be formed from either the material of the first layer or the material of the second layer. Methods for fabricating the fuse include forming the first and second layers and patterning the first and second layers so as to form a fuse with the desired structure.Type: GrantFiled: March 16, 2005Date of Patent: September 16, 2008Assignee: Micron Technology, Inc.Inventor: Kenneth W. Marr
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Patent number: 7405463Abstract: According to embodiments of the present invention, circuits have elements to protect a high-voltage transistor in a gate dielectric antifuse circuit. An antifuse has a layer of gate dielectric between a first terminal coupled to receive an elevated voltage and a second terminal, and a high-voltage transistor is coupled to the antifuse and has a gate terminal. An intermediate voltage between the supply voltage and the elevated voltage is coupled to the gate terminal of the high-voltage transistor to protect the high-voltage transistor.Type: GrantFiled: June 26, 2006Date of Patent: July 29, 2008Assignee: Micron Technology, Inc.Inventors: Kenneth W. Marr, John D. Porter
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Patent number: 7369379Abstract: A combination of a current limiting resistor and a clamping Schottky diode prevent substantial forward biasing of a pn junction associated with a pad in a snapback device during normal operation, but do not substantially affect triggering of the device during an unbiased electrostatic discharge event. Minority carrier injection from n+ devices is substantially reduced, and the circuit may also be used to clamp an oxide voltage in a thin oxide semiconductor device.Type: GrantFiled: May 3, 2006Date of Patent: May 6, 2008Assignee: Micron Technology, Inc.Inventor: Kenneth W. Marr
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Patent number: 7279918Abstract: A method, circuit and system for determining burn-in reliability from wafer level burn-in are disclosed. The method includes recording the number of failures in each IC die in nonvolatile elements on-chip at points in time over the duration of wafer level burn-in testing. Methods may also include using a super voltage level to signal a transition between cycles of burn-in testing. The number of failures in each IC die, along with their associated points in time, may be used to create burn-in reliability curves which are conventionally derived using other processes that may be less cost effective or not possible to effect with unpackaged IC dice. Unused registers of nonvolatile elements may also be determined by reading the nonvolatile element registers on a semiconductor die on the wafer. Circuits and systems associated with the method of the present invention are also disclosed.Type: GrantFiled: September 26, 2006Date of Patent: October 9, 2007Assignee: Micron Technology, Inc.Inventor: Kenneth W. Marr
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Patent number: 7215134Abstract: A method, circuit and system for determining burn-in reliability from wafer level burn-in are disclosed. The method according to the present invention includes recording the number of failures in each IC die in nonvolatile elements on-chip at points in time over the duration of wafer level burn-in testing. The number of failures in each IC die, along with their associated points in time, may be used to create burn-in reliability curves which are conventionally derived using other processes that may be less cost effective or not possible to effect with unpackaged IC dice. Circuits and systems associated with the method of the present invention are also disclosed.Type: GrantFiled: May 16, 2005Date of Patent: May 8, 2007Assignee: Micron Technology, Inc.Inventor: Kenneth W. Marr
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Patent number: 7183792Abstract: A threshold detection circuit for developing a mode trigger signal includes an input that receives an input signal. In response to the input signal having approximately an input threshold value for a triggering time, the threshold detection circuit activates the mode trigger signal on an output. In response to the input signal being substantially different from the input threshold value or the input signal not having the input threshold value for the triggering time, the circuit deactivates the mode trigger signal. The threshold detection circuit may be contained in a variety of different mode detection circuits for detecting when an integrated circuit is to be placed in a test mode or other desired mode of operation, and such mode detection circuits may be contained in a variety of different types of integrated circuits, such as memory devices generally and SRAMs specifically.Type: GrantFiled: April 1, 2003Date of Patent: February 27, 2007Assignee: Micron Technology, Inc.Inventor: Kenneth W. Marr
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Patent number: 7126871Abstract: According to embodiments of the present invention, an antifuse circuit is operated by coupling an elevated voltage to a first terminal of an antifuse, controlling current in the antifuse with a program driver circuit coupled to a second terminal of the antifuse, and shunting current around the antifuse with a bypass circuit coupled between the first terminal of the antifuse and the program driver circuit to protect the antifuse. The antifuse includes a layer of gate dielectric between the first terminal and the second terminal. The embodiments of the present invention protect a gate dielectric antifuse.Type: GrantFiled: February 3, 2004Date of Patent: October 24, 2006Assignee: Micron Technology, Inc.Inventors: Kenneth W. Marr, John D. Porter
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Patent number: 7123042Abstract: A large-scale support carries semiconductor devices and at least one pair of common conductive regions in communication therewith. Each common conductive region is configured to be electrically connected with both a force contact and a sense contact of stress or test equipment. Such equipment includes at least one pair of force contacts for applying a force voltage across a pair of common conductive regions and, thus, across the support. A corresponding pair of sense contacts facilitates monitoring of a voltage applied across each of the semiconductor devices by the force contacts. Methods and systems for evaluating a voltage that has been applied to two or more semiconductor devices by way of a single pair of force contacts are also disclosed, as are methods and systems for, in response to a measured voltage, modifying the force voltage so that a desired voltage may be applied across each of the semiconductor devices.Type: GrantFiled: February 9, 2005Date of Patent: October 17, 2006Assignee: Micron Technology, Inc.Inventor: Kenneth W. Marr